VHDL实现简易计算器Word文件下载.docx
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VHDL实现简易计算器Word文件下载.docx
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integerrange0to7;
signalL2,LL2,LLL2,LLLL2:
integerrange0to10;
signalL1,LL1,LLL1,LLLL1:
signalL,LL,LLL,LLLL:
signalnn:
integerrange0to9999;
signalbi:
integerrange0to20000;
begin
分频模块
process(clr,clk)
variablec:
ifclr=‘0’thenc:
=0;
elsifrising_edge(clk)then
ifc<
10thenc:
=c+1;
elsec:
endif;
ifc>
5thensec1<
=‘1’;
elsesec1<
=‘0’;
endprocess;
process(clr,clk)
variablec:
integerrange0to3200000;
begin
3200000thenc:
=1;
1600000thensec_1_10<
elsesec_1_10<
键控模块
process(sec_1_10,clr,mul,div,sub,add,set)
variablecc,dd:
std_logic;
variablep,pp:
integerrange0to3;
variablem:
variabled,e,f,g:
integerrange0to9;
variableee:
integerrange0to90;
variableff:
integerrange0to900;
variablegg:
integerrange0to9000;
ifclr=‘0’or((mul=‘0’ordiv=‘0’orsub=‘0’oradd=‘0’)andset=‘1’andch=‘1’)
thenc:
d:
e:
f:
g:
ee:
ff:
gg:
m:
p:
cc:
dd:
pp:
elsifrising_edge(sec_1_10)then
ifdent=‘1’then
ifm<
7thenm:
=m+1;
elsem:
=7;
elsifset=‘0’andadd=‘0’thendd:
elsifdd=‘1’then
ifpp<
3thenpp:
=pp+1;
elsepp:
dd:
elsifdiv=‘0’andset=‘0’thencc:
elsifcc=‘1’then
ifp<
3thenp:
=p+1;
elsep:
=3;
cc:
elsifch=‘0’then
5thenc:
elsifc=2andset=‘0’then
ifd<
9thend:
=d+1;
elsed:
elsifc=3andset=‘0’then
ife<
9thene:
=e+1;
=ee+10;
elsee:
elsifc=4andset=‘0’then
iff<
9thenf:
=f+1;
ff:
=ff+100;
elsef:
elsifc=5andset=‘0’then
ifg<
9theng:
=g+1;
gg:
=gg+1000;
elseg:
elsenull;
choose<
=c;
L1<
=d;
LL1<
=e;
LLL1<
=f;
LLLLL1<
=g;
nn<
=d+ee+ff+gg;
chose<
=m;
get<
=p;
minus_sig<
=pp;
运算及存储模块
process(clr,sec1,bi)
variableminmmin:
variablead,sb,mu,dv:
std_logic_vector(1downto0);
variablec,d,f,g,m:
ifclr=‘0’thenmin:
c:
bi<
sb:
=“00”;
ad:
mu:
dv:
outrange<
elsifrising_edge(sec1)then
ifset=‘0’andmul=‘0’thenmmin:
=min;
ifad:
=“00”andsb:
=“00”andmu:
=“00”anddv:
=“00”thenm:
=nn;
=bi;
elsifset=‘0’anddiv=‘0’thenbi<
d:
min:
=mmin;
ad:
=“10”;
elsifminus_sig=3thenmin:
=not(min);
elsifsub=‘0’andset=‘1’thensb:
=“01”;
elsifadd=‘0’andset=‘1’thenad:
sb:
elsifmul=‘0’andset=‘1’thenmu:
f:
g:
elsifdiv=‘0’andset=‘1’thendv:
mu:
elsifdent=‘0’andad=“00”andsb=“00”andmu=“00”anddv=“00”thend:
elsif(ad=“10”orsb=“10”ormu=“10”ordv=“10”)anddent=‘0’thend:
elsifsb=“10”anddent=‘1’thenc:
ifmin=‘1’thensb:
ifd>
=cthend:
=d-c;
elsemin:
=c-d;
elsif(c+d)<
10000thensb:
=(c+d);
elseoutrange<
=‘0’;
elsifad=“01”anddent=‘1’thenc:
ifmin=‘1’thenad:
if(c+d)<
10000thend:
=(c+d);
elsifc<
dthenbi<
=“10”;
=‘1’;
elsifmu=“01”anddent=‘1’thenc:
ifc=0ord=0thenbi<
elsiff<
ctheng:
=g+d;
ifg>
9999thenbi<
outrange<
elsebi<
elsifdv=“01”anddent=‘1’thenc:
ifc=0thenbi<
elsifc=1thenbi<
elsifd>
=cthen
20000thend:
elsifd<
c/2thenbi<
dv:
=f+1;
minus<
process(get,sec1,clr,mul,div,sub,add,bi,set)
variablecc,dd,ee:
integerrange0to10;
variablebb:
integerrange0to20000;
ifclr=‘0’or((mul=‘0’ordiv=‘0’orsub=‘0’oradd=‘0’)andset=‘1’andch=‘1’)orget=1
thencc:
ee:
bb:
ifchose=5orget=2thenbb:
elsifbb>
999thencc:
=cc+1;
bb:
=bb-1000;
elsif
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- VHDL 实现 简易 计算器