EDA实验程序.docx
- 文档编号:12659558
- 上传时间:2023-04-21
- 格式:DOCX
- 页数:15
- 大小:70.63KB
EDA实验程序.docx
《EDA实验程序.docx》由会员分享,可在线阅读,更多相关《EDA实验程序.docx(15页珍藏版)》请在冰豆网上搜索。
EDA实验程序
实验1--一位全加器的设计======
--程序1:
或门逻辑描述
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYor2aIS
PORT(a,b:
INSTD_LOGIC;
c:
OUTSTD_LOGIC);
ENDENTITYor2a;
ARCHITECTUREoneOFor2aIS
BEGIN
c<=aORb;
ENDARCHITECTUREone;
--程序2:
半加器描述
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_adderIS
PORT(a,b:
INSTD_LOGIC;
co,so:
OUTSTD_LOGIC);
ENDENTITYh_adder;
ARCHITECTUREfh1OFh_adderis
BEGIN
so<=NOT(aXOR(NOTb));
co<=aANDb;
ENDARCHITECTUREfh1;
--程序3:
1位二进制全加器顶层设计描述
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYf_adderIS
PORT(ain,bin,cin:
INSTD_LOGIC;
cout,sum:
OUTSTD_LOGIC);
ENDENTITYf_adder;
ARCHITECTUREfd1OFf_adderIS
COMPONENTh_adder
PORT(a,b:
INSTD_LOGIC;
co,so:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTor2a
PORT(a,b:
INSTD_LOGIC;
c:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALd,e,f:
STD_LOGIC;
BEGIN
u1:
h_adderPORTMAP(a=>ain,b=>bin,
co=>d,so=>e);
u2:
h_adderPORTMAP(a=>e,b=>cin,
co=>f,so=>sum);
u3:
or2aPORTMAP(a=>d,b=>f,c=>cout);
ENDARCHITECTUREfd1;
实验2--原理图输入法设计8位全加器
半加器
一位的全加器
八位的全加器
实验3--含异步清0和同步时钟使能的4位加法计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadderis
port(reset:
instd_logic;
clkin:
instd_logic;
coutge:
outstd_logic_vector(3downto0);
coutshi:
outstd_logic_vector(3downto0));
endadder;
architectureshiyan3ofadderis
signaltemp:
std_logic_vector(3downto0);
signaltemp1:
std_logic_vector(3downto0);
begin
process(clkin,reset)
begin
if(reset='1')thentemp<=(others=>'0');temp1<=(others=>'0');
elsifrising_edge(clkin)then
if(temp1>="1001")
thentemp<=(others=>'0');temp1<=(others=>'0');
elsiftemp>="1001"then
temp<=(others=>'0');temp1<=temp1+1;
else
temp<=temp+1;
endif;
endif;
coutge<=temp;
coutshi<=temp1;
endprocess;
endshiyan3;
=========
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT10IS
PORT(CLK,RST,EN:
INSTD_LOGIC;
CQ:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
COUT:
OUTSTD_LOGIC);
ENDCNT10;
ARCHITECTUREbehavOFCNT10IS
BEGIN
PROCESS(CLK,RST,EN)
VARIABLECQI:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
IFRST='1'THENCQI:
=(OTHERS=>'0');--计数器复位
ELSIFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿
IFEN='1'THEN--检测是否允许计数
IFCQI<"1001"THENCQI:
=CQI+1;--允许计数
ELSECQI:
=(OTHERS=>'0');--大于9,计数值清零
ENDIF;
ENDIF;
ENDIF;
IFCQI="1001"THENCOUT<='1';--计数大于9,输出进位信号
ELSECOUT<='0';
ENDIF;
CQ<=CQI;--将计数值向端口输出
ENDPROCESS;
ENDbehav;
实验4==数控分频器===========
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYPULSEIS
PORT(CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
FOUT:
OUTSTD_LOGIC);
ENDPULSE;
ARCHITECTUREoneOFPULSEIS
SIGNALFULL:
STD_LOGIC;
BEGIN
P_REG:
PROCESS(CLK)
VARIABLECNT8:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFCNT8="11111111"THEN
CNT8:
=D;
FULL<='1';
ELSECNT8:
=CNT8+1;
FULL<='0';
ENDIF;
ENDIF;
ENDPROCESSP_REG;
P_DIV:
PROCESS(FULL)
VARIABLECNT2:
STD_LOGIC;
BEGIN
IFFULL'EVENTANDFULL='1'THEN
CNT2:
=NOTCNT2;
IFCNT2='1'THENFOUT<='1';
ELSEFOUT<='0';
ENDIF;
ENDIF;
ENDPROCESSP_DIV;
END;
实验5--用状态机实现序列检测器的设计
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSCHKIS
PORT(DIN,CLK,CLR:
INSTD_LOGIC;--串行输入数据位/工作时钟/复位信号
AB:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));--检测结果输出
ENDSCHK;
ARCHITECTUREbehavOFSCHKIS
SIGNALQ:
INTEGERRANGE0TO8;
SIGNALD:
STD_LOGIC_VECTOR(7DOWNTO0);--8位待检测预置数
BEGIN
D<="11100101";--8位待检测预置数
PROCESS(CLK,CLR)
BEGIN
IFCLR='1'THENQ<=0;
ELSIFCLK'EVENTANDCLK='1'THEN--时钟到来时,判断并处理当前输入的位
CASEQIS
WHEN0=>IFDIN=D(7)THENQ<=1;ELSEQ<=0;ENDIF;
WHEN1=>IFDIN=D(6)THENQ<=2;ELSEQ<=0;ENDIF;
WHEN2=>IFDIN=D(5)THENQ<=3;ELSEQ<=0;ENDIF;
WHEN3=>IFDIN=D(4)THENQ<=4;ELSEQ<=0;ENDIF;
WHEN4=>IFDIN=D(3)THENQ<=5;ELSEQ<=0;ENDIF;
WHEN5=>IFDIN=D
(2)THENQ<=6;ELSEQ<=0;ENDIF;
WHEN6=>IFDIN=D
(1)THENQ<=7;ELSEQ<=0;ENDIF;
WHEN7=>IFDIN=D(0)THENQ<=8;ELSEQ<=0;ENDIF;
WHENOTHERS=>Q<=0;
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS(Q)--检测结果判断输出
BEGIN
IFQ=8THENAB<="1010";--序列数检测正确,输出"A"
ELSEAB<="1011";--序列数检测错误,输出"B"
ENDIF;
ENDPROCESS;
ENDbehav;
实验6--用状态机对ADC0809的采样控制电路实现
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYADCINTIS
PORT(D:
INSTD_LOGIC_VECTOR(7DOWNTO0);--0809的8位转换数据输出
CLK,EOC:
INSTD_LOGIC;--CLK是转换工作时钟
LOCK1,ALE,START,OE,ADDA:
OUTSTD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDADCINT;
ARCHITECTUREbehavOFADCINTIS
TYPEstatesIS(st0,st1,st2,st3,st4,st5,st6);--定义各状态子类型
SIGNALcurrent_state,next_state:
states:
=st0;
SIGNALREGL:
STD_LOGIC_VECTOR(7DOWNTO0);
SIGNALLOCK:
STD_LOGIC;--转换后数据输出锁存时钟信号
BEGIN
ADDA<='1';LOCK1<=LOCK;
PRO:
PROCESS(current_state,EOC)BEGIN--规定各状态转换方式
CASEcurrent_stateIS
WHENst0=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<=st1;
WHENst1=>ALE<='1';START<='0';OE<='0';LOCK<='0';next_state<=st2;
WHENst2=>ALE<='0';START<='1';OE<='0';LOCK<='0';next_state<=st3;
WHENst3=>ALE<='0';START<='0';OE<='0';LOCK<='0';
IF(EOC='1')THENnext_state<=st3;--测试EOC的下降沿
ELSEnext_state<=st4;
ENDIF;
WHENst4=>ALE<='0';START<='0';OE<='0';LOCK<='0';
IF(EOC='0')THENnext_state<=st4;--测试EOC的上升沿,=1表明转换结束
ELSEnext_state<=st5;--继续等待
ENDIF;
WHENst5=>ALE<='0';START<='0';OE<='1';LOCK<='0';next_state<=st6;
WHENst6=>ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<=st0;
WHENOTHERS=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<=st0;
ENDCASE;
ENDPROCESSPRO;
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
current_state<=next_state;--在时钟上升沿,转换至下一状态
ENDIF;
ENDPROCESS;--由信号current_state将当前状态值带出此进程,进入进程PRO
PROCESS(LOCK)--此进程中,在LOCK的上升沿,将转换好的数据锁入
BEGIN
IFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;
ENDIF;
ENDPROCESS;
Q<=REGL;
ENDbehav;
实验7原理图输入设计含LPM的电路
实验8===循环冗余
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.ALL;
USEieee.std_logic_arith.ALL;
ENTITYcrcmIS
PORT(clk:
INstd_logic;
sdata:
INstd_logic_vector(11DOWNTO0);
datald:
INstd_logic;
datacrco:
OUTstd_logic_vector(16DOWNTO0);
datacrci:
INstd_logic_vector(16DOWNTO0);
rdata:
OUTstd_logic_vector(11DOWNTO0);
datafini:
OUTstd_logic;
ERROR0,hsend:
OUTstd_logic;
hrecv:
INstd_logic);
ENDcrcm;
ARCHITECTUREcommOFcrcmIS
CONSTANTmulti_coef:
std_logic_vector(5DOWNTO0):
="110101";
--多项式系数,MSB一定为'1'
SIGNALcnt:
std_logic_vector(4DOWNTO0);
SIGNALdtemp:
std_logic_vector(11DOWNTO0);
SIGNALsdatam:
std_logic_vector(11DOWNTO0);
SIGNALrdtemp:
std_logic_vector(11DOWNTO0);
SIGNALrdatacrc:
std_logic_vector(16DOWNTO0);
SIGNALrcnt:
std_logic_vector(4DOWNTO0);
SIGNALst:
std_logic;
SIGNALrt:
std_logic;
BEGIN
PROCESS(clk)
VARIABLEcrcvar:
std_logic_vector(5DOWNTO0);
BEGIN
IF(clk'eventANDclk='1')THEN
IF(st='0'ANDdatald='1')THEN
dtemp<=sdata;sdatam<=sdata;
cnt<=(OTHERS=>'0');
hsend<='0';st<='1';
ELSIF(st='1'ANDcnt<7)THEN
cnt<=cnt+1;
IF(dtemp(11)='1')THEN
crcvar:
=dtemp(11DOWNTO6)XORmulti_coef;
dtemp<=crcvar(4DOWNTO0)&dtemp(5DOWNTO0)&'0';
ELSEdtemp<=dtemp(10DOWNTO0)&'0';
ENDIF;
ELSIF(st='1'ANDcnt=7)THEN
datacrco<=sdatam&dtemp(11DOWNTO7);
hsend<='1';cnt<=cnt+1;
ELSIF(st='1'ANDcnt=8)THEN
hsend<='0';st<='0';
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(hrecv,clk)
VARIABLErcrcvar:
std_logic_vector(5DOWNTO0);
BEGIN
IF(clk'eventANDclk='1')THEN
IF(rt='0'ANDhrecv='1')THEN
rdtemp<=datacrci(16DOWNTO5);
rdatacrc<=datacrci;rcnt<=(OTHERS=>'0');
ERROR0<='0';rt<='1';
ELSIF(rt='1'ANDrcnt<7)THEN
datafini<='0';rcnt<=rcnt+1;
rcrcvar:
=rdtemp(11DOWNTO6)XORmulti_coef;
IF(rdtemp(11)='1')THEN
rdtemp<=rcrcvar(4DOWNTO0)&rdtemp(5DOWNTO0)&'0';
ELSErdtemp<=rdtemp(10DOWNTO0)&'0';
ENDIF;
ELSIF(rt='1'ANDrcnt=7)THEN
datafini<='1';
rdata<=rdatacrc(16DOWNTO5);
rt<='0';
IF(rdatacrc(4DOWNTO0)/=rdtemp(11DOWNTO7))THEN
ERROR0<='1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDcomm;
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA 实验 程序