电子密码锁的设计外文翻译.docx
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电子密码锁的设计外文翻译.docx
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电子密码锁的设计外文翻译
外文文献译文
设计(论文)题目:
电子密码锁的设计
专业与班级:
测控技术与仪器0602班
学生姓名:
于良
指导教师:
周彬
2007年3月18日
IntroductionofAT89C51
Description:
TheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standardMCS-51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theATMELCo.’sAT89C51isapowerfulmicrocomputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.
Features:
·CompatiblewithinstructionsetofMCS-51products
·4Kbytesofin-systemreprogrammableFlashmemory
·Endurance:
1000write/erasecycles
·Dataretentiontime:
10years
·Fullystaticoperation:
0Hzto24MHz
·Three-levelprogrammemorylock
·128×8-bitinternalRAM
·32programmableI/Olines
·Two16-bitTimer/Counters
·Sixinterruptsource
·Programmableserialchannel
·Low-poweridleandPower-downmodes
·On-chiposcillatorandclockcircuitry
·Full-duplexUARTserialportinterruptline
·DualDataPointerRegister
FunctionCharacteristicDescription:
TheAT89C51providesthefollowingstandardfeatures:
4KbytesofFlashmemory,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.
The8051microcontrollerisanindustrystandardarchitecturethathasbroadacceptance,wide-rangingapplicationsanddevelopmenttoolsavailable.Therearenumerouscommercialvendorsthatsupplythiscontrollerorhaveitintegratedintosometypeofsystem-on-a-chipstructure.BothMRCandIAμEchosethisdevicetodemonstratetwodistinctlydifferenttechnologiesforhardening.TheMRCexampleofthisistousetemporallatchesthatrequirespecifictimingtoensurethatsingleeventeffectsareminimized.TheIAμEtechnologyusesultralowpower,andlayoutandarchitectureHBDdesignrulestoachievetheirresults.ThesearefundamentallydifferentthantheapproachbyAeroflex-UnitedTechnologiesMicroelectronicsCenter(UTMC),thecommercialvendorofaradiation–hardened8051,thatbuilttheir8051microcontrollerusingradiationhardenedprocesses.Thisbroadrangeoftechnologywithinonedevicestructuremakesthe8051anidealvehicleforperformingthistechnologyevaluation
PinDescription:
·VCC:
Supplyvoltage
·GND:
Ground
·Port0:
Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.
Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/busduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.
Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.
·Port1:
Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
·Port2:
Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.
Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorywhichuses16-bitaddresses(MOVX@DPTR).Inthisapplication,itusesstronginternalpullupswhenemitting1s.Duringaccessestoexternaldatamemorywhichuses8-bitaddresses(MOVX@RI).Port2emitsthecontentsoftheP2SpecialFunctionRegister.
Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
·Port3:
Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.WhentheP3Iwrite"1"after,theyareinternalpull-upishigh,andusedasinput.Asinput,duetotheexternalpull-downforthelow,P3portoutputcurrent(ILL)Thisisduetopull-up'ssake.
Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:
Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.
·RST:
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.
·ALE/
:
AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(
)duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.
Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
·
:
ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,
isactivatedtwiceeachmachinecycle,exceptthattwo
activationsareskippedduringeachaccesstoexternaldatamemory.
·/EA/VPP:
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.When/EAtomaintainlow,thenduringthisperiodtheexternalprogrammemory(0000H-FFFFH),regardlessofwhetheraninternalprogrammemory.
Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.
·XTAL1:
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
·XTAL2:
Outputfromtheinvertingoscillatoramplifier.
·Ready/
:
TheprogressofbyteprogrammingcanalsobemonitoredbytheRDY/
outputsignal.P3.4ispulledlowafterALEgoeshighduringprogrammingtoindicateBUSY.P3.4ispulledhighagainwhenprogrammingisdonetoindicateREADY.
OscillatorCharacteristics:
XTAL1andXTAL2respectively,reverseamplifierinputandoutput.Thereverseamplifiercanbeconfiguredason-chiposcillator.ShiJingoscillationandceramicoscillationcanbeused.Ifusinganexternalclocksourcedrivethedevice,XTAL2shouldnottake.Morethaninputtotheinternalclocksignalthroughatwo-wayflip-flop,sotheexternalclocksignalpulsewidthwithoutanyrequest,butmustensurethatthehigh-lowpulsewidthrequirements.
ClockOscillator:
XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.
Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdriven.
Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadividebytwofliptrigger,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
IdleMode:
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.
Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.
Power-downMode:
Inthepower-downmode,theoscillatorisstopped,andtheinstructionthatinvokespower-downisthelastinstructionexecuted.Theon-chipRAMandspecialfunctionregistersretaintheirvaluesuntilthepower-downmodeisterminated.Theonlyexitfrompower-downisahardwarereset.Resetredefinesthespecialfunctionregistersbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormal
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