基于AT89C52控制的电热恒温系统中英文翻译资料.docx

基于AT89C52控制的电热恒温系统中英文翻译资料.docx

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基于AT89C52控制的电热恒温系统中英文翻译资料

英文原文

Description

Theat89s52isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemory（PEROM）and128bytesRAM.ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51™instructionsetandpinout.Thechipcombinesaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelat89s52isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.

Features:

•CompatiblewithMCS-51™Products

•4KBytesofIn-SystemReprogrammableFlashMemory

•Endurance:

1,000Write/EraseCycles

•FullyStaticOperation:

0Hzto24MHz

•Three-LevelProgramMemoryLock

•128x8-BitInternalRAM

•32ProgrammableI/OLines

•Two16-BitTimer/Counters

•SixInterruptSources

•ProgrammableSerialChannel

•LowPowerIdleandPowerDownModes

Theat89s52providesthefollowingstandardfeatures:

4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theat89s52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.

PinDescription:

VCCSupplyvoltage.

GNDGround.

Port0

Port0isan8-bitopendrainbidirectionalI/Oport.AsanoutputporteachpincansinkeightTTLinputs.Whenisarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.

Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.

Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.

Port1

Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpullups.

Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2

Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpullups.

Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses（MOVX@DPTR）.Inthisapplicationitusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses（MOVX@RI）,Port2emitsthecontentsoftheP2SpecialFunctionRegister.

Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3

Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseofthepullups.

Port3alsoservesthefunctionsofvariousspecialfeaturesoftheat89s52aslistedbelow:

Portpin

alternatefunctions

P3.0

rxd（serialinputport）

P3.1

txd（serialoutputport）

P3.2

^int0（externalinterrupt0）

P3.3

^int1（externalinterrupt1）

P3.4

t0（timer0externalinput）

P3.5

t1（timer1externalinput）

P3.6

^WR（externaldatamemorywritestrobe）

P3.7

^rd（externaldatamemoryreadstrobe）

Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.

RST

Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.

ALE/PROG

AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput（PROG）duringFlashprogramming.

InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.

Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.

PSEN

ProgramStoreEnableisthereadstrobetoexternalprogrammemory.

Whentheat89s52isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.

EA/VPP

ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.

EAshouldbestrappedtoVCCforinternalprogramexecutions.

Thispinalsoreceivesthe12-voltprogrammingenablevoltage（VPP）duringFlashprogramming,forpartsthatrequire12-voltVPP.

XTAL1

Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.

XTAL2

Outputfromtheinvertingoscillatoramplifier.

OscillatorCharacteristics

XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.

IdleMode

Inidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.

Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.

StatusofExternalPinsDuringIdleandPowerDownModes

mode

Programmemory

ALE

^psen

Port0

Port1

Port2

Port3

idle

internal

1

1

data

data

data

Data

Idle

External

1

1

float

Data

data

Data

Powerdown

Internal

0

0

Data

Data

Data

Data

Powerdown

External

0

0

float

data

Data

data

PowerDownMode

Inthepowerdownmodetheoscillatorisstopped,andtheinstructionthatinvokespowerdownisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.

ProgramMemoryLockBits

Onthechiparethreelockbitswhichcanbeleftunprogrammed（U）orcanbeprogrammed（P）toobtaintheadditionalfeatureslistedinthetablebelow:

LockBitProtectionModes

Whenlockbit1isprogrammed,thelogiclevelattheEApinissampledandlatchedduringreset.Ifthedeviceispoweredupwithoutareset,thelatchinitializestoarandomvalue,andholdsthatvalueuntilresetisactivated.ItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly.

ProgrammingtheFlash：

Theat89s52isnormallyshippedwiththeon-chipFlashmemoryarrayintheerasedstate（thatis,contents=FFH）andreadytobeprogrammed.Theprogramminginterfaceacceptseitherahigh-voltage（12-volt）oralow-voltage（VCC）programenablesignal.Thelowvoltageprogrammingmodeprovidesaconvenientwaytoprogramtheat89s52insidetheuser’ssystem,whilethehigh-voltageprogrammingmodeiscompatiblewithconventionalthirdpartyFlashorEPROMprogrammers.

Theat89s52isshippedwitheitherthehigh-voltageorlow-voltageprogrammingmodeenabled.Therespectivetop-sidemarkinganddevicesignaturecodesarelistedinthefollowingtable.

Vpp=12v

Vpp=5v

Top-sidemark

at89s52

xxxx

yyww

at89s52

xxxx-5

yyww

signature

（030H）=1EH

（031H）=51H

（032H）=FFH

（030H）=1EH

（031H）=51H

（032H）=05H

Theat89s52codememory