eda考试程序.docx

eda考试程序.docx

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eda考试程序

1：

用VHDL语言设计2选1多路选择器。

ENTITYmux21aIS

PORT（a,b,s:

INBIT;

y:

OUTBIT）;

ENDENTITYmux21a;

ARCHITECTUREoneOFmux21aIS

BEGIN

y<=aWHENs='0'ELSEb;

ENDARCHITECTUREone;

2：

将此二选一多路选择器看成是一个元件mux21a，利用元件例化语

句描述图1.1所示双2选1多路选择器，并将此文件放在同一目录中。

ENTITYMUXKIS

PORT（a1,a2,a3,s0,s1:

INBIT;

outy:

OUTBIT）;

ENDENTITYMUXK;

ARCHITECTUREoneOFMUXKIS

COMPONENTmux21a

PORT（a,b,s:

INBIT;

y:

OUTBIT）;

ENDCOMPONENT;

SIGNALtmp:

BIT;

BEGIN

U1:

mux21aPORTMAP（a=>a2,b=>a3,s=>s0,y=>tmp）;

U2:

mux21aPORTMAP（a=>a1,b=>tmp,s=>s1,y=>outy）;

ENDARCHITECTUREone;

实验二时序逻辑电路的VHDL设计

3：

用VHDL语言设计D边沿触发器。

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYDFF1IS

PORT（CLK:

INSTD_LOGIC;

D:

INSTD_LOGIC;

Q:

OUTSTD_LOGIC）;

END;

ARCHITECTUREbhvOFDFF1IS

SIGNALQ1:

STD_LOGIC;

BEGIN

PROCESS（CLK,Q1）

BEGIN

IFCLK'EVENTANDCLK='1'

THENQ1<=D;

ENDIF;

ENDPROCESS;

Q<=Q1;

ENDbhv;

4：

用VHDL语言设计D锁存器。

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYDFF3IS

PORT（CLK:

INSTD_LOGIC;

D:

INSTD_LOGIC;

Q:

OUTSTD_LOGIC）;

END;

ARCHITECTUREbhvOFDFF3IS

BEGIN

PROCESS（CLK,D）

BEGIN

IFCLK='1'

THENQ<=D;

ENDIF;

ENDPROCESS;

ENDbhv;

实验三一般计数器的VHDL设计

5：

用VHDL设计含异步清0和同步时钟使能的十进制加法计数器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYCNT10IS

PORT（CLK,RST,EN:

INSTD_LOGIC;

CQ:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC）;

ENDCNT10;

ARCHITECTUREBEHAVOFCNT10IS

BEGIN

PROCESS（CLK,RST,EN）

VARIABLECQI:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

IFRST='1'THENCQI:

=（OTHERS=>'0'）;

ELSIFCLK'EVENTANDCLK='1'THEN

IFEN='1'THEN

IFCQI<9THENCQI:

=CQI+1;

ELSECQI:

=（OTHERS=>'0'）;

ENDIF;

ENDIF;

ENDIF;

IFCQI=9THENCOUT<='1';

ELSECOUT<='0';

ENDIF;

CQ<=CQI;

ENDPROCESS;

ENDBEHAV;

6：

用VHDL设计含异步清0和同步时钟使能的十进制加减可控计数器。

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYCNTIS

PORT（CLK,RST,EN,UD:

INSTD_LOGIC;

CQ:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC）;

ENDCNT;

ARCHITECTUREBEHAVOFCNTIS

BEGIN

PROCESS（CLK,RST,EN,UD）

VARIABLECQI:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

IFRST='1'THENCQI:

=（OTHERS=>'0'）;

ELSIFCLK'EVENTANDCLK='1'THEN

IFEN='1'THEN

IFUD='0'THEN

IFCQI<9THENCQI:

=CQI+1;

ELSECQI:

=（OTHERS=>'0'）;

ENDIF;

ENDIF;

IFUD='1'THEN

IFCQI=0THENCQI:

="1001";

ELSIFCQI<10THENCQI:

=CQI-1;

ELSECQI:

="1001";

--ENDIF;

ENDIF;

ENDIF;

ENDIF;

ENDIF;

IFUD='0'THEN

IFCQI=9THENCOUT<='1';

ELSECOUT<='0';

ENDIF;

ENDIF;

IFUD='1'THEN

IFCQI=0THENCOUT<='1';

ELSECOUT<='0';

ENDIF;

ENDIF;

CQ<=CQI;

ENDPROCESS;

ENDBEHAV;

实验四计数、译码显示电路的VHDL设计

7：

用VHDL语言设计七段数码显示译码器，实现16进制数的译码显示。

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

--USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYDECL7SIS

PORT（A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

LED7S:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

END;

ARCHITECTUREONEOFDECL7SIS

BEGIN

PROCESS（A）

BEGIN

CASEAIS

WHEN"0000"=>LED7S<="0111111";

WHEN"0001"=>LED7S<="0000110";

WHEN"0010"=>LED7S<="1011011";

WHEN"0011"=>LED7S<="1001111";

WHEN"0100"=>LED7S<="1100110";

WHEN"0101"=>LED7S<="1101101";

WHEN"0110"=>LED7S<="1111101";

WHEN"0111"=>LED7S<="0000111";

WHEN"1000"=>LED7S<="1111111";

WHEN"1001"=>LED7S<="1101111";

WHEN"1010"=>LED7S<="1110111";

WHEN"1011"=>LED7S<="1111100";

WHEN"1100"=>LED7S<="0111001";

WHEN"1101"=>LED7S<="1011110";

WHEN"1110"=>LED7S<="1111001";

WHEN"1111"=>LED7S<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

ENDPROCESS;

8：

用VHDL语言描述图4.1所示计数、译码显示电路。

（DEC）

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYDECIS

PORT（CLK0,RST0,ENA0:

INSTD_LOGIC;

LED:

OUTSTD_LOGIC_VECTOR（6DOWNTO0）;

COUT0:

OUTSTD_LOGIC）;

ENDDEC;

ARCHITECTUREONEOFDECIS

COMPONENTCNT16IS

PORT（CLK,RST,ENA:

INSTD_LOGIC;

CQ:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUTY:

OUTSTD_LOGIC）;

ENDCOMPONENT;

COMPONENTDECL7SIS

PORT（A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

LED7S:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDCOMPONENT;

SIGNALTMP:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

U1:

CNT16PORTMAP（CLK=>CLK0,RST=>RST0,ENA=>ENA0,CQ=>TMP,COUTY=>COUT0）;

U2:

DECL7SPORTMAP（A=>TMP,LED7S=>LED）;

END;

（CNT16）

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYCNT16IS

PORT（CLK,RST,ENA:

INSTD_LOGIC;

CQ:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUTY:

OUTSTD_LOGIC）;

ENDCNT16;

ARCHITECTUREBEHAVOFCNT16IS

BEGIN

PROCESS（CLK,RST,ENA）

VARIABLECQI:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

IFRST='1'THENCQI:

=（OTHERS=>'0'）;

ELSIFCLK'EVENTANDCLK='1'THEN

IFENA='1'THEN

IFCQI<15THENCQI:

=CQI+1;

ELSECQI:

=（OTHERS=>'0'）;

ENDIF;

ENDIF;

ENDIF;

IFCQI=15THENCOUTY<='1';

ELSECOUTY<='0';

ENDIF;

CQ<=CQI;

ENDPROCESS;

ENDBEHAV;

实验五8位数码扫描显示电路的VHDL设计

9：

用VHDL语言设计8位数码扫描显示电路，显示输出数据直接在程序中给出。

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYsmxsIS

PORT（AI:

INOUTSTD_LOGIC_VECTOR（2DOWNTO0）;

CLK,RST,EN:

INSTD_LOGIC;

A:

INOUTSTD_LOGIC_VECTOR（3DOWNTO0）;

--A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

K:

OUTSTD_LOGIC_VECTOR（7DOWNTO0）;

--CQ:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC;

LED7S:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

END;

ARCHITECTUREoneOFsmxsIS

SIGNALPASS:

STD_LOGIC_VECTOR（2DOWNTO0）;

BEGIN

js:

PROCESS（CLK,RST,EN）

VARIABLECQI:

STD_LOGIC_VECTOR（2DOWNTO0）;

BEGIN

IFRST='1'THENCQI:

=（OTHERS=>'0'）;

ELSIFCLK'EVENTANDCLK='1'THEN

IFEN='1'THEN

IFCQI<7THENCQI:

=CQI+1;

ELSECQI:

=（OTHERS=>'0'）;

ENDIF;

ENDIF;

ENDIF;

IFCQI=7THENCOUT<='1';

ELSECOUT<='0';

ENDIF;

PASS<=CQI;

ENDPROCESSjs;

AI<=PASS;

sm:

PROCESS（AI）

BEGIN

IFAI="000"THENK<="00000001";

ELSIFAI="001"THENK<="00000010";

ELSIFAI="010"THENK<="00000100";

ELSIFAI="011"THENK<="00001000";

ELSIFAI="100"THENK<="00010000";

ELSIFAI="101"THENK<="00100000";

ELSIFAI="110"THENK<="01000000";

ELSEK<="10000000";

ENDIF;

ENDPROCESSsm;

A<="1000";

xs:

PROCESS（A）

BEGIN

CASEAIS

WHEN"0000"=>LED7S<="0111111";

WHEN"0001"=>LED7S<="0000110";

WHEN"0010"=>LED7S<="1011011";

WHEN"0011"=>LED7S<="1001111";

WHEN"0100"=>LED7S<="1100110";

WHEN"0101"=>LED7S<="1101101";

WHEN"0110"=>LED7S<="1111101";

WHEN"0111"=>LED7S<="0000111";

WHEN"1000"=>LED7S<="1111111";

WHEN"1001"=>LED7S<="1101111";

WHEN"1010"=>LED7S<="1110111";

WHEN"1011"=>LED7S<="1111100";

WHEN"1100"=>LED7S<="0111001";

WHEN"1101"=>LED7S<="1011110";

WHEN"1110"=>LED7S<="1111001";

WHEN"1111"=>LED7S<="1110001";

WHENOTHERS=>NULL;

ENDCASE;

ENDPROCESSxs;

ENDone;

10：

修改实验内容1的程序，增加8个4位锁存器作为输

出显示数据缓冲器，由外部输入8个待显示的十六进制数。

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYSMSCXSIS

PORT（AI:

INOUTSTD_LOGIC_VECTOR（2DOWNTO0）;

--CLK:

INSTD_LOGIC;

CLK0,CLK1,CLK2:

INSTD_LOGIC;

D0:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

A:

INOUTSTD_LOGIC_VECTOR（3DOWNTO0）;

--A:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

K:

OUTSTD_LOGIC_VECTOR（7DOWNTO0）;

--COUT:

OUTSTD_LOGIC;

LED7S:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

--Q0:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

END;

ARCHITECTUREoneOFSMSCXSIS

COMPONENTD4

PORT（CLK:

INSTD_LOGIC;

D:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

Q:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDCOMPONENT;

SIGNALPASS:

STD_LOGIC_VECTOR（2DOWNTO0）;

SIGNALP0,P1,P2,P3,P4,P5,P6,P7:

STD_LOGIC_VECTOR（3DOWNTO0）;

SIGNALD1,D2,D3,D9,D5,D6,D7,D8:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

SC:

PROCESS（CLK2）

VARIABLEQI:

STD_LOGIC_VECTOR（2DOWNTO0）;

BEGIN

--IFRST='1'THENCQI:

=（OTHERS=>'0'）;

IFCLK2'EVENTANDCLK2='1'THEN

--IFEN='1'THEN

IFQI<7THENQI:

=QI+1;

ELSEQI:

=（OTHERS=>'0'）;

ENDIF;

--ENDIF;

ENDIF;

--IFCQI=7THENCOUT<='1';

--ELSECOUT<='0';

--ENDIF;

--PASS<=QI;

CASEQIIS

WHEN"000"=>D1<=D0;

WHEN"001"=>D2<=D0;

WHEN"010"=>D3<=D0;

WHEN"011"=>D9<=D0;

WHEN"100"=>D5<=D0;

WHEN"101"=>D6<=D0;

WHEN"110"=>D7<=D0;

WHEN"111"=>D8<=D0;

WHENOTHERS=>NULL;

ENDCASE;

ENDPROCESSSC;

U1:

D4PORTMAP（CLK=>CLK1,D=>D1,Q=>P0）;

U2:

D4PORTMAP（CLK=>CLK1,D=>D2,Q=>P1）;

U3:

D4PORTMAP（CLK=>CLK1,D=>D3,Q=>P2）;

U4:

D4PORTMAP（CLK=>CLK1,D=>D9,Q=>P3）;

U5:

D4PORTMAP（CLK=>CLK1,D=>D5,Q=>P4）;

U6:

D4PORTMAP（CLK=>CLK1,D=>D6,Q=>P5）;

U7:

D4PORTMAP（CLK=>CLK1,D=>D7,Q=>P6）;

U8:

D4PORTMAP（CLK=>CLK1,D=>D8,Q=>P7）;

js:

PROCESS（CLK0）

VARIABLECQI:

STD_LOGIC_VECTOR（2DOWNTO0）;

BEGIN

--IFRST='1'THENCQI:

=（OTHERS=>'0'）;

IFCLK0'EVENTANDCLK0='1'THEN

--IFEN='1'THEN

IFCQI<7THENCQI:

=CQI+1;

ELSECQI:

=（OTHERS=>'0'）;

ENDIF;

--ENDIF;

ENDIF;

--IFCQI=7THENCOUT<='1';

--ELSECOUT<='0';

--ENDIF;

PASS<=CQI;

ENDPROCESSjs;

AI<=PASS;

sm:

PROCESS（AI）

BEGIN

IFAI="000"THENK<="00000001";A<=P0;

ELSIFAI="001"THENK<="00000010";A<=P1;

ELSIFAI="010"THENK<="00000100";A<=P2;

ELSIFAI="011"THENK<="00001000";A<=P3;

ELSIFAI="100"THENK<="00010000";A<=P4;

ELSIFAI="101"THENK<="00100000";A<=P5;

ELSIFAI="110"THENK<="01000000";A<=P6;

ELSEK<="10000000";A<=P7;

ENDIF;

ENDPROCESSsm;

xs:

PROCESS（A）

BEGIN

CASEAIS

WHEN"0000"=>LED7S<="0111111";

WHEN"0001"=>LED7S<="0000110";

WH