eda程序.docx
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- 上传时间:2023-04-16
- 格式:DOCX
- 页数:50
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eda程序.docx
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eda程序
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
entityclockis
port(clk:
instd_logic;
seg_tmp:
outstd_logic_VECTOR(6downto0);
dig_tmp:
outSTD_LOGIC_VECTOR(3DOWNTO0));
endclock;
ARCHITECTUREa1OFclockIS
SIGNALsec:
STD_LOGIC;
SIGNALnum:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALp:
STD_LOGIC;
SIGNALtmp:
STD_LOGIC_VECTOR(23DOWNTO0);
SIGNALcount3bit:
integerrange0to2;
SIGNALtm1,tm2,tm3,tm4:
std_logic_vector(3downto0);
SIGNALseg:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALdig_clk:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
process(clk)
begin
ifclk'eventandclk='1'thentmp<=tmp+1;
endif;
p<=tmp(23);
dig_clk<=tmp(18downto17);
endprocess;
process(p)
begin
ifp'eventandp='1'then
ifcount3bit=2then
sec<='1';
count3bit<=0;
else
sec<='0';
count3bit<=count3bit+1;
endif;
endif;
endprocess;
process(sec)
begin
ifsec'eventandsec='1'then
iftm1="1001"then
tm1<="0000";
iftm2="0101"then
tm2<="0000";
iftm3="1001"then
tm3<="0000";
iftm4="0101"then
tm4<="0000";
elsetm4<=tm4+1;
endif;
elsetm3<=tm3+1;
endif;
elsetm2<=tm2+1;
endif;
elsetm1<=tm1+1;
endif;
endif;
endprocess;
process(dig_clk)
begin
casedig_clkis
when"00"=>seg<=tm1;
when"01"=>seg<=tm2;
when"10"=>seg<=tm3;
when"11"=>seg<=tm4;
endcase;
endprocess;
process(seg)
begin
casesegis
when"0000"=>seg_tmp<="1000000";
when"0001"=>seg_tmp<="1111001";
when"0010"=>seg_tmp<="0100100";
when"0011"=>seg_tmp<="0110000";
when"0100"=>seg_tmp<="0011001";
when"0101"=>seg_tmp<="0010010";
when"0110"=>seg_tmp<="0000010";
when"0111"=>seg_tmp<="1111000";
when"1000"=>seg_tmp<="0000000";
when"1001"=>seg_tmp<="0010000";
whenothers=>seg_tmp<="ZZZZZZZ";
endcase;
endprocess;
process(dig_clk)
begin
casedig_clkis
when"00"=>dig_tmp<="1110";
when"01"=>dig_tmp<="1101";
when"10"=>dig_tmp<="1011";
when"11"=>dig_tmp<="0111";
endcase;
endprocess;
enda1;
只有分和秒的
输入1Hz的时钟作为秒信号,秒计数满60后向分计数进1,分计数满60后向时计数进1。
当计数到24:
60:
60自动回到00:
00:
00;
libraryieee;
useieee.std_logic_1164.all;
entityclockis
port(clk:
instd_logic;--输入1Hz的时钟作为秒信号
clr:
instd_logic;--异步清零信号
s:
outintegerrange0to60;--秒
min:
outintegerrange0to60;--分
h:
outintegerrange0to24--时
);
endclock;
architectureclockofclockis
begin
process(clk,clr)
variablecount1:
integerrange0to60;--秒计数
variablecount2:
integerrange0to60;--分计数
variablecount3:
integerrange0to24;--时计数
begin
s<=count1;
min<=count2;
h<=count3;
if(clr='1')then
count1:
=0;
count2:
=0;
count3:
=0;
elsif(clk'eventandclk='1')then
count1:
=count1+1;
if(count1=60)then
count1:
=0;
count2:
=count2+1;
if(count2=60)then
count2:
=0;
count3:
=count3+1;
if(count3=24)then
count3:
=0;
endif;
endif;
endif;
endif;
endprocess;
endclock;
源代码如下自己把各个模块打好包下面有个图自己看看
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYTZKZQIS
PORT(KEY:
INSTD_LOGIC_VECTOR(1DOWNTO0);--按键信号
CLK_KEY:
INSTD_LOGIC;--键盘扫描信号
MAX_DAYS:
INSTD_LOGIC_VECTOR(4DOWNTO0);--本月最大天数
SEC_EN,MIN_EN,HOUR_EN,DAY_EN,MON_EN,YEAR_EN,WEEK_EN:
OUTSTD_LOGIC;--异步并行置位使能
HOUR_CUR:
INSTD_LOGIC_VECTOR(4DOWNTO0);
MIN_CUR,SEC_CUR:
INSTD_LOGIC_VECTOR(5DOWNTO0);
YEAR_CUR:
INSTD_LOGIC_VECTOR(6DOWNTO0);
MON_CUR:
INSTD_LOGIC_VECTOR(3DOWNTO0);
DAY_CUR:
INSTD_LOGIC_VECTOR(4DOWNTO0);
WEEK_CUR:
INSTD_LOGIC_VECTOR(2DOWNTO0);
SEC,MIN:
BUFFERSTD_LOGIC_VECTOR(5DOWNTO0);
HOUR:
BUFFERSTD_LOGIC_VECTOR(4DOWNTO0);
DAY:
BUFFERSTD_LOGIC_VECTOR(4DOWNTO0);
MON:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0);
YEAR:
BUFFERSTD_LOGIC_VECTOR(6DOWNTO0);
WEEK:
BUFFERSTD_LOGIC_VECTOR(2DOWNTO0));
ENDENTITYTZKZQ;
ARCHITECTUREARTOFTZKZQIS
TYPESTATETYPEIS(NORMAL,SEC_SET,MIN_SET,HOUR_SET,DAY_SET,MON_SET,
YEAR_SET,WEEK_SET);
SIGNALMODE:
STATETYPE;
BEGIN
PROCESS(KEY,CLK_KEY)
BEGIN
IFCLK_KEY'EVENTANDCLK_KEY='1'THEN
IFKEY="01"THEN
SEC_EN<='1';MIN_EN<='1';HOUR_EN<='1';
DAY_EN<='1';MON_EN<='1';YEAR_EN<='1';
WEEK_EN<='1';
CASEMODEIS
WHENNORMAL=>MODE<=SEC_SET;SEC<=SEC_CUR;SEC_EN<='0';
WHENSEC_SET=>MODE<=MIN_SET;MIN<=MIN_CUR;SEC_EN<='1';MIN_EN<='0';
WHENMIN_SET=>MODE<=HOUR_SET;HOUR<=HOUR_CUR;MIN_EN<='1';HOUR_EN<='0';
WHENHOUR_SET=>MODE<=DAY_SET;DAY<=DAY_CUR;HOUR_EN<='1';DAY_EN<='0';
WHENDAY_SET=>MODE<=MON_SET;MON<=MON_CUR;DAY_EN<='1';MON_EN<='0';
WHENMON_SET=>MODE<=YEAR_SET;YEAR<=YEAR_CUR;MON_EN<='1';
YEAR_EN<='0';
WHENYEAR_SET=>MODE<=WEEK_SET;WEEK<=WEEK_CUR;YEAR_EN<='1';WEEK_EN<='0';
WHENWEEK_SET=>MODE<=NORMAL;
ENDCASE;
ELSIFKEY="10"THEN--如果按下调整键,则自加
CASEMODEIS
WHENSEC_SET=>SEC_EN<='0';
--异步并行置位使能有效
IFSEC="111011"THENSEC<="000000";
--如果秒计数到59,返回到0重新计数
ELSESEC<=SEC+1;--否则继续计数
ENDIF;
WHENMIN_SET=>MIN_EN<='0';
IFMIN="111011"THENMIN<="000000";
ELSEMIN<=MIN+1;
ENDIF;
WHENHOUR_SET=>HOUR_EN<='0';
IFHOUR="11000"THENHOUR<="00000";
ELSEHOUR<=HOUR+1;
ENDIF;
WHENDAY_SET=>DAY_EN<='0';
IFDAY=MAX_DAYSTHENDAY<="00001";
ELSEDAY<=DAY+1;
ENDIF;
WHENWEEK_SET=>WEEK_EN<='0';
IFWEEK="111"THENWEEK<="001";
ELSEWEEK<=WEEK+1;
ENDIF;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT60IS
PORT(LD:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR(5DOWNTO0);
NUM:
BUFFERSTD_LOGIC_VECTOR(5DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDENTITYCNT60;
ARCHITECTUREARTOFCNT60IS
BEGIN
PROCESS(CLK,LD)IS
BEGIN
IF(LD='0')THEN
NUM<=DATA;
ELSIFCLK'EVENTANDCLK='1'THEN
IFNUM="111011"THEN--59
NUM<="000000";CO<='1';
ELSE
NUM<=NUM+1;CO<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT60IS
PORT(LD:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR(5DOWNTO0);
NUM:
BUFFERSTD_LOGIC_VECTOR(5DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDENTITYCNT60;
ARCHITECTUREARTOFCNT60IS
BEGIN
PROCESS(CLK,LD)IS
BEGIN
IF(LD='0')THEN
NUM<=DATA;
ELSIFCLK'EVENTANDCLK='1'THEN
IFNUM="111011"THEN--59
NUM<="000000";CO<='1';
ELSE
NUM<=NUM+1;CO<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT24IS
PORT(LD:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR(4DOWNTO0);
NUM:
BUFFERSTD_LOGIC_VECTOR(4DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDENTITYCNT24;
ARCHITECTUREARTOFCNT24IS
BEGIN
PROCESS(CLK,LD)IS
BEGIN
IF(LD='0')THEN
NUM<=DATA;
ELSIFCLK'EVENTANDCLK='1'THEN
IFNUM="11000"THEN--24
NUM<="00000";CO<='1';
ELSE
NUM<=NUM+1;CO<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT30IS
PORT(LD:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
NIAN:
INSTD_LOGIC_VECTOR(6DOWNTO0);
YUE:
INSTD_LOGIC_VECTOR(3DOWNTO0);
DATA:
INSTD_LOGIC_VECTOR(4DOWNTO0);
NUM:
BUFFERSTD_LOGIC_VECTOR(4DOWNTO0);
MAX_DAYS:
OUTSTD_LOGIC_VECTOR(4DOWNTO0);
CO:
OUTSTD_LOGIC);
ENDENTITYCNT30;
ARCHITECTUREARTOFCNT30IS
SIGNALTOTAL_DAYS:
STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
PROCESS(CLK,LD)IS
VARIABLEIS_RUNNIAN:
STD_LOGIC;
BEGIN
CASENIANIS
WHEN"0000000"=>IS_RUNNIAN:
='1';--0
WHEN"0000100"=>IS_RUNNIAN:
='1';--4
WHEN"0001000"=>IS_RUNNIAN:
='1';--8
WHEN"0001100"=>IS_RUNNIAN:
='1';--12
WHEN"0010000"=>IS_RUNNIAN:
='1';--16
WHEN"0010100"=>IS_RUNNIAN:
='1';--20
WHEN"0011000"=>IS_RUNNIAN:
='1';--24
WHEN"0011100"=>IS_RUNNIAN:
='1';--28
WHEN"0100000"=>IS_RUNNIAN:
='1';--32
WHEN"0100100"=>IS_RUNNIAN:
='1';--36
WHEN"0101000"=>IS_RUNNIAN:
='1';--40
WHEN"0101100"=>IS_RUNNIAN:
='1';--44
WHEN"0110000"=>IS_RUNNIAN:
='1';--48
WHEN"0110100"=>IS_RUNNIAN:
='1';--52
WHEN"0111000"=>IS_RUNNIAN:
='1';--56
WHEN"0111100"=>IS_RUNNIAN:
='1';--60
WHEN"1000000"=>IS_RUNNIAN:
='1';--64
WHEN"1000100"=>IS_RUNNIAN:
='1';--68
WHEN"1001000"=>IS_RUNNIAN:
='1';--72
WHEN"1001100"=>IS_RUNNIAN:
='1';--76
WHEN"1010000"=>IS_RUNNIAN:
='1';--80
WHEN"1010100"=>IS_RUNNIAN:
='1';--84
WHEN"1011000"=>IS_RUNNIAN:
='1';--88
WHEN"1011100"=>IS_RUNNIAN:
='1';--92
WHEN"1100000"=>IS_RUNNIAN:
='1';--96
WHENOTHERS=>IS_RUNNIAN:
='0';
ENDCASE;
CASEYUEIS
WHEN"0001"=>TOTAL_DAYS<="11111";--1
WHEN"0011"=>TOTAL_DAYS<="11111";--3
WHEN"0101"=>TOTAL_DAYS<="11111";--5
WHEN"0111"=>TOTAL_DAYS<="11111";--7
WHEN"1000"=>TOTAL_DAYS<="11111";--8
WHEN"1010"=>TOTAL_DAYS<="11111";--10
WHEN"1100"=>TOTAL_DAYS<="11111";--12
WHEN"0100"=>TOTAL_DAYS<="11110";--4
WHEN"0110"=>TOTAL_DAYS<="11110";--6
WHEN"1001"=>TOTAL_DAYS<="11110";--9
WHEN"1011"=>TOTAL_DAYS<="11110";--11
WHEN"0010"=>
IF(IS_RUNNIAN='1')THEN
TOTAL_DAYS<="11101";
ELSE
TOTAL_DAYS<="11100";
ENDIF;
WHENOTHERS=>NULL;
ENDCASE;
IF(LD='0')THEN
NUM<=DATA;
ELSIFCLK'EVENTANDCLK='1'THEN
MAX_DAYS<=TOTAL_DAYS;
IFNUM=TOTAL_DAYSTHEN--99
NUM<="00001";CO<='1';
ELSE
NUM<=NUM+1;CO<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT7IS
PORT(LD:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR(2DOWNTO0);
NUM:
BUFFERSTD_LOGIC_VECTOR(2DOWNTO0));
ENDENTITYCNT7;
ARCHITECTUREARTOFCNT7IS
BEGIN
PROCESS(CLK,LD)IS
BEGIN
IF(LD='0')THEN
NUM<=DATA;
ELSIFCLK'EVENTANDCLK='1'THEN
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