数字电子技术(Floyd 第十版)课件Chapter -07-st1-.ppt
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数字电子技术(Floyd 第十版)课件Chapter -07-st1-.ppt
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,DigitalFundamentalsTenthEditionFloyd,Chapter7,2008PearsonEducation,Alatchisatemporarystoragedevicethathastwostablestates(bistable).Itisabasicformofmemory.,Summary,Latches,TheS-R(Set-Reset)latchisthemostbasictype.ItcanbeconstructedfromNORgatesorNANDgates.WithNORgates,thelatchrespondstoactive-HIGHinputs;withNANDgates,itrespondstoactive-LOWinputs.,NORActive-HIGHLatchNANDActive-LOWLatch,R,S,Q,Q,Theactive-HIGHS-Rlatchisinastable(latched)conditionwhenbothinputsareLOW.,Summary,Latches,AssumethelatchisinitiallyRESET(Q=0)andtheinputsareattheirinactivelevel(0).ToSETthelatch(Q=1),amomentaryHIGHsignalisappliedtotheSinputwhiletheRremainsLOW.,0,1,0,1,0,0,ToRESETthelatch(Q=0),amomentaryHIGHsignalisappliedtotheRinputwhiletheSremainsLOW.,0,0,1,0,1,0,LatchinitiallyRESET,LatchinitiallySET,Theactive-LOWS-Rlatchisinastable(latched)conditionwhenbothinputsareHIGH.,Summary,Latches,Q,1,1,0,1,0,1,LatchinitiallyRESET,Q,1,1,0,1,0,1,LatchinitiallySET,Neverapplyanactivesetandresetatthesametime(invalid).,Theactive-LOWS-Rlatchisavailableasthe74LS279AIC.,Summary,Latches,1Q,2Q,3Q,4Q,74LS279A,Agatedlatchisavariationonthebasiclatch.,Summary,Latches,Thegatedlatchhasanadditionalinput,calledenable(EN)thatmustbeHIGHinorderforthelatchtorespondtotheSandRinputs.,R,S,Q,EN,ShowtheQoutputwithrelationtotheinputsignals.AssumeQstartsLOW.,Example,Solution,KeepinmindthatSandRareonlyactivewhenENisHIGH.,S,R,EN,Q,Summary,Latches,TheDlatchisanvariationoftheS-RlatchbutcombinestheSandRinputsintoasingleDinputasshown:
AsimplerulefortheDlatchis:
QfollowsDwhentheEnableisactive.,D,EN,Q,Q,D,EN,Summary,Latches,ThetruthtablefortheDlatchsummarizesitsoperation.IfENisLOW,thenthereisnochangeintheoutputanditislatched.,Summary,Latches,DeterminetheQoutputfortheDlatch,giventheinputsshown.,Q,D,EN,Example,Summary,Flip-flops,Aflip-flopdiffersfromalatchinthemanneritchangesstates.Aflip-flopisaclockeddevice,inwhichonlytheclockedgedetermineswhenanewbitisentered.Theactiveedgecanbepositiveornegative.,Dynamicinputindicator,Summary,Flip-flops,Thetruthtableforapositive-edgetriggeredDflip-flopshowsanuparrowtoremindyouthatitissensitivetoitsDinputonlyontherisingedgeoftheclock;otherwiseitislatched.Thetruthtableforanegative-edgetriggeredDflip-flopisidenticalexceptforthedirectionofthearrow.,(a)Positive-edgetriggered(b)Negative-edgetriggered,Summary,Flip-flops,TheJ-Kflip-flopismoreversatilethantheDflipflop.Inadditiontotheclockinput,ithastwoinputs,labeledJandK.WhenbothJandK=1,theoutputchangesstates(toggles)ontheactiveclockedge(inthiscase,therisingedge).,Summary,Flip-flops,DeterminetheQoutputfortheJ-Kflip-flop,giventheinputsshown.,Example,CLK,Q,K,J,CLK,K,J,Q,Noticethattheoutputschangeontheleadingedgeoftheclock.,Solution,Set,Toggle,Set,Latch,Summary,Flip-flops,CLK,D,CLK,Q,Dflip-flophardwiredforatogglemode,Summary,Flip-flops,Synchronousinputsaretransferredinthetriggeringedgeoftheclock(forexampletheDorJ-Kinputs).Mostflip-flopshaveotherinputsthatareasynchronous,meaningtheyaffecttheoutputindependentoftheclock.,Twosuchinputsarenormallylabeledpreset(PRE)andclear(CLR).TheseinputsareusuallyactiveLOW.AJ-KflipflopwithactiveLOWpresetandCLRisshown.,CLK,K,J,Q,PRE,CLR,Summary,Flip-flops,Flip-flops,DeterminetheQoutputfortheJ-Kflip-flop,giventheinputsshown.,Example,CLK,K,J,Q,PRE,CLR,Solution,Set,Toggle,Reset,Toggle,Set,Set,Reset,Latch,CLK,K,J,Q,Propagationdelaytimeisspecifiedfortherisingandfallingoutputs.Itismeasuredbetweenthe50%leveloftheclocktothe50%leveloftheoutputtransition.,Summary,Flip-flopCharacteristics,50%pointontriggeringedge,50%point,50%pointonLOW-to-HIGHtransitionofQ,tPLH,tPHL,CLK,CLK,Q,Q,50%pointonHIGH-to-LOWtransitionofQ,Thetypicalpropagationdelaytimeforthe74AHCfamily(CMOS)is4ns.Evenfasterlogicisavailableforspecializedapplications.,Anotherpropagationdelaytimespecificationisthetimerequiredforanasynchronousinputtocauseachangeintheoutput.Againitismeasuredfromthe50%levels.The74AHCfamilyhasspecifieddelaytimesunder5ns.,Summary,Flip-flopCharacteristics,50%point,tPLH,tPHL,Q,50%point,50%point,50%point,Q,PRE,CLR,Set-uptimeandholdtimearetimesrequiredbeforeandaftertheclocktransitionthatdatamustbepresenttobereliablyclockedintotheflip-flop.,Summary,Flip-flopCharacteristics,Setuptimeistheminimumtimeforthedatatobepresentbeforetheclock.,Holdtimeistheminimumtimeforthedatatoremainaftertheclock.,CLK,D,CLK,D,Set-uptime,ts,Holdtime,tH,Otherspecificationsincludemaximumclockfrequency,minimum
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