TMS320C645xDSPDDR2MemoryController精.docx
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TMS320C645xDSPDDR2MemoryController精.docx
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TMS320C645xDSPDDR2MemoryController精
TMS320C645xDSP
DDR2MemoryControllerUser'sGuide
LiteratureNumber:
SPRU970F
December2005–RevisedMay2010
2SPRU970F–December2005–RevisedMay2010
Copyright©2005–2010,TexasInstrumentsIncorporated
Preface(6
1Introduction(7
1.1PurposeofthePeripheral(7
1.2Features(7
1.3FunctionalBlockDiagram(7
1.4IndustryStandard(sComplianceStatement(8
2PeripheralArchitecture(9
2.1ClockControl(9
2.2MemoryMap(9
2.3SignalDescriptions(9
2.4ProtocolDescription(s(11
2.5MemoryWidth,ByteAlignment,andEndianness(18
2.6AddressMapping(19
2.7DDR2MemoryControllerInterface(22
2.8RefreshScheduling(25
2.9Self-RefreshMode(26
2.10ResetConsiderations(26
2.11DDR2SDRAMMemoryInitialization(26
2.12InterruptSupport(28
2.13EDMAEventSupport(28
2.14EmulationConsiderations(28
3UsingtheDDR2MemoryController(29
3.1ConnectingtheDDR2MemoryControllertoDDR2SDRAM(29
3.2ConfiguringDDR2MemoryControllerRegisterstoMeetDDR2SDRAMSpecifications(33
4DDR2MemoryControllerRegisters(36
4.1ModuleIDandRevisionRegister(MIDR(37
4.2DDR2MemoryControllerStatusRegister(DMCSTAT(38
4.3SDRAMConfigurationRegister(SDCFG(39
4.4SDRAMRefreshControlRegister(SDRFC(41
4.5SDRAMTiming1Register(SDTIM1(42
4.6SDRAMTiming2Register(SDTIM2(44
4.7BurstPriorityRegister(BPRIO(45
4.8DDR2MemoryControllerControlRegister(DMCCTL(46
AppendixARevisionHistory(47
3SPRU970F–December2005–RevisedMay2010TableofContents
Copyright©2005–2010,TexasInstrumentsIncorporated
ListofFigures
1DeviceBlockDiagram(8
2DDR2MemoryControllerSignals(10
3DDR2MRSandEMRSCommand(12
4RefreshCommand(13
5ACTVCommand(14
6DCABCommand(15
7DEACCommand(16
8DDR2READCommand(17
9DDR2WRTCommand(18
10ByteAlignment(19
11LogicalAddress-to-DDR2SDRAMAddressMapfor32-BitSDRAM(20
12LogicalAddress-to-DDR2SDRAMAddressMapfor16-bitSDRAM(20
13LogicalAddress-to-DDR2SDRAMAddressMap(21
14DDR2SDRAMColumn,Row,andBankAccess(22
15DDR2MemoryControllerFIFOBlockDiagram(23
16ConnectingtoTwo16-BitDDR2SDRAMDevices(30
17ConnectingtoaSingle16-BitDDR2SDRAMDevice(31
18ConnectingtoTwo8-BitDDR2SDRAMDevices(32
19ModuleIDandRevisionRegister(MIDR(37
20DDR2MemoryControllerStatusRegister(DMCSTAT(38
21SDRAMConfigurationRegister(SDCFG(39
22SDRAMRefreshControlRegister(SDRFC(41
23SDRAMTiming1Register(SDTIM1(42
24SDRAMTiming2Register(SDTIM2(44
25BurstPriorityRegister(BPRIO(45
26DDR2MemoryControllerControlRegister(DMCCTL(46
4ListofFiguresSPRU970F–December2005–RevisedMay2010
Copyright©2005–2010,TexasInstrumentsIncorporated
ListofTables
1DDR2MemoryControllerSignalDescriptions(10
2DDR2SDRAMCommands(11
3TruthTableforDDR2SDRAMCommands(11
4AddressableMemoryRanges(18
5BankConfigurationRegisterFieldsforAddressMapping(19
6DDR2MemoryControllerFIFODescription(22
7RefreshUrgencyLevels(25
8DeviceandDDR2MemoryControllerResetRelationship(26
9DDR2SDRAMModeRegisterConfiguration(27
10DDR2SDRAMExtendedModeRegister1Configuration(27
11SDCFGConfiguration(33
12DDR2MemoryRefreshSpecification(34
13SDRFCConfiguration(34
14SDTIM1Configuration(34
15SDTIM2Configuration(35
16DMCCTLConfiguration(35
17DDR2MemoryControllerRegisters(36
18ModuleIDandRevisionRegister(MIDRFieldDescriptions(37
19DDR2MemoryControllerStatusRegister(DMCSTATFieldDescriptions(38
20SDRAMConfigurationRegister(SDCFGFieldDescriptions(39
21SDRAMRefreshControlRegister(SDRFCFieldDescriptions(41
22SDRAMTiming1Register(SDTIM1FieldDescriptions(42
23SDRAMTiming2Register(SDTIM2FieldDescriptions(44
24BurstPriorityRegister(BPRIOFieldDescriptions(45
25DDR2MemoryControllerControlRegister(DMCCTLFieldDescriptions(46
26DDR2RevisionHistory(47
5SPRU970F–December2005–RevisedMay2010ListofTables
Copyright©2005–2010,TexasInstrumentsIncorporated
Preface
SPRU970F–December2005–RevisedMay2010
ReadThisFirst
AboutThisManual
ThisdocumentdescribestheDDR2memorycontrollerintheTMS320C645xdigitalsignalprocessors
(DSPs.
NotationalConventions
Thisdocumentusesthefollowingconventions.
•Hexadecimalnumbersareshownwiththesuffixh.Forexample,thefollowingnumberis40hexadecimal(decimal64:
40h.
•Registersinthisdocumentareshowninfiguresanddescribedintables.
–Eachregisterfigureshowsarectangledividedintofieldsthatrepresentthefieldsoftheregister.
Eachfieldislabeledwithitsbitname,itsbeginningandendingbitnumbersabove,andits
read/writepropertiesbelow.Alegendexplainsthenotationusedfortheproperties.
–Reservedbitsinaregisterfiguredesignateabitthatisusedforfuturedeviceexpansion.
RelatedDocumentationFromTexasInstruments
ThefollowingdocumentsdescribetheC6000™devicesandrelatedsupporttools.Copiesofthese
documentsareavailableontheInternet.Tip:
Entertheliteraturenumberinthesearchboxprovidedat.
SPRU189—TMS320C6000DSPCPUandInstructionSetReferenceGuide.DescribestheCPUarchitecture,pipeline,instructionset,andinterruptsfortheTMS320C6000digitalsignalprocessors
(DSPs.
SPRU198—TMS320C6000Programmer'sGuide.DescribeswaystooptimizeCandassemblycodefortheTMS320C6000™DSPsandincludesapplicationprogramexamples.
SPRU301—TMS320C6000CodeComposerStudioTutorial.IntroducestheCodeComposerStudio™integrateddevelopmentenvironmentandsoftwaretools.
SPRU321—CodeComposerStudioApplicationProgrammingInterfaceReferenceGuide.
DescribestheCodeComposerStudio™applicationprogramminginterface(API,whichallowsyou
toprogramcustomplug-insforCodeComposer.
SPRU871—TMS320C64x+MegamoduleReferenceGuide.DescribestheTMS320C64x+digitalsignalprocessor(DSPmegamodule.Includedisadiscussionontheinternaldirectmemoryaccess
(IDMAcontroller,theinterruptcontroller,thepower-downcontroller,memoryprotection,bandwidth
management,andthememoryandcache.
C6000,TMS320C6000,CodeComposerStudioaretrademarksofTexasInstruments.
Allothertrademarksarethepropertyoftheirrespectiveowners.
6PrefaceSPRU970F–December2005–RevisedMay2010
User'sGuide
SPRU970F–December2005–RevisedMay2010
C645xDDR2MemoryController
1Introduction
1.1PurposeofthePeripheral
TheDDR2memorycontrollerisusedtointerfacewithJESD79-2BstandardcompliantDDR2SDRAM
devices.MemorytypessuchasDDR1SDRAM,SDRSDRAM,SBSRAM,andasynchronousmemoriesarenotsupported.TheDDR2memorycontrollerSDRAMcanbeusedforprogramanddatastorage.
1.2Features
TheDDR2memorycontrollersupportsthefollowingfeatures:
•JESD79-2BstandardcompliantDDR2SDRAM
•512Mbytememoryspace
•Databuswidthof32or16bits
•CASlatencies:
2,3,4,and5
•Internalbanks:
1,2,4,and8
•Burstlength:
8
•Bursttype:
sequential
•1CEsignal
•Pagesizes:
256,512,1024,and2048
•SDRAMautoinitialization
•Self-refreshmode
•Prioritizedrefresh
•Programmablerefreshrateandbacklogcounter
•Programmabletimingparameters
•Littleendianandbigendiantransfers
1.3FunctionalBlockDiagram
TheDDR2memorycontrolleristhemaininterfacetoexternalDDR2memory(seeFigure1.Master
peripherals,suchastheEDMAcontrollerandtheCPUcanaccesstheDDR2memorycontrollerthroughtheswitchedcentralresource(SCR.TheDDR2memorycontrollerperformsallmemory-related
backgroundtaskssuchasopeningandclosingbanks,refreshes,andcommandarbitration.
Introduction
Figure1.DeviceBlockDiagram
1.4IndustryStandard(sComplianceStatement
TheDDR2memorycontrolleriscompliantwiththeJESD79-2BDDR2SDRAM.
8C645xDDR2MemoryControllerSPRU970F–December2005–RevisedMay2010
PeripheralArchitecture2PeripheralArchitecture
TheDDR2memorycontrollercangluelesslyinterfacetomoststandardDDR2SDRAMdevicesand
supportssuchfeaturesasself-refreshmodeandprioritizedrefresh.Inaddition,itprovidesflexibility
throughprogrammableparameterssuchastherefreshrate,CASlatency,andmanySDRAMtiming
parameters.
ThefollowingsectionsdescribethearchitectureoftheDDR2memorycontrolleraswellashowto
interfaceandconfigureittoperformreadandwriteoperationstoDDR2SDRAMdevices.Also,Section3providesadetailedexampleofinterfacingtheDDR2memorycontrollertoacommonDDR2SDRAM
device.
2.1ClockControl
TheDDR2memorycontrollerisclockeddirectlyfromtheoutputofthesecondphase-lockedloop(PLL2ofC645xdevices.ThePLL2multipliesitsinputclockby20.Thisclockisdividedby2togenerate
DDR2CLKOUT.ThefrequencyofDDR2CLKOUTcanbedeterminedbyusingthefollowingformula:
DDR2CLKOUTfrequency=(PLL2inputclockfrequency×20/2=PLL2inputclockfrequency×10
ThesecondoutputclockoftheDDR2memorycontroller,DDR2CLKOUT,istheinverseof
DDR2CLKOUT.FormoreinformationonthePLL2,seethedevice-specificdatamanual.
2.2MemoryMap
Forinformationdescribingthedevicememorymap,seethedevice-specificdatamanual.
2.3SignalDescriptions
TheDDR2memorycontrollersignalsareshowninFigure2anddescribedinTable1.Thefollowing
featuresareincluded:
•Themaximumwidthforthedatabus(DED[31:
0]is32-bits.
•Theaddressbus(DEA[13:
0]is14-bitswidewithanadditional3bankaddresspins(DBA[2:
0].
•Twodifferentialoutputclocks(DDR2CLKOUTandDDR2CLKOUTdrivenbyinternalclocksources.
•Commandsignals:
Rowandcolumnaddressstrobe(DSDRASandDSDCAS,writeenablestrobe(DSDWE,datastrobe(DSDDQS[3:
0]andDSDDQS[3:
0],anddatamask(DSDDQM[3:
0].
•Onechipselectsignal(DCE0.
•Oneclockenablesignal(DSDCKE.
•Twoon-dieterminationoutputsignals(DEODT[1:
0].
PeripheralArchitecture
Figure2.DDR2MemoryControllerSignals
Table1.DDR2MemoryControllerSignalDescriptions
PinDescription
DED[31:
0]Bidirectionaldatabus.Inputfordatareadsandoutput
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