数字电子钟的设计说明.docx
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数字电子钟的设计说明.docx
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数字电子钟的设计说明
摘要及关键字······························································2
ABSTRACT··································································2
一.设计要求·······························································2
二.总体方案设计···························································3
三.各子模块设计原理·······················································3
1.计秒模块······························································3
2.计分模块······························································5
3.计时模块······························································6
4.校准模块······························································7
5.显示模块······························································9
6.报时模块······························································12
7.分频模块······························································13
8.去抖动模块····························································15
四.硬件下载与测试························································16
1.硬件下载······························································16
2.测试··································································17
3.功能扩展······························································17
五.结论···································································17
参考文献··································································18
数字电子钟的设计
摘要及关键字:
数字电子钟是生活中最常用的电子设备之一,其主要功能是能够显示时、分、秒实时信息,并能够方便地进行时、分、秒的初始值设置,以便时间校准。
实现数字电子钟有很多方法,本课程是采用VHDL硬件语言的强大描述能力和EDA工具的结合在电子设计领域来设计一个具有多功能的数字电子钟。
关键字:
数字电子钟VHDL硬件语言EDA工具
ABSTRACT:
Digitalelectricclockinlifearethemostcommonlyusedoneoftheelectronicequipment.Itsmainfunctionistodisplay,minutesandsecondsreal-timeinformationandcanbeeasilywhencarriedout,minutesandseconds,sothattheinitialvalueissettimecalibration.
Therearemanymethodsofdesigndigitalelectricclock.ThiscourseisapowerfulbyVHDLhardwarelanguagedescribeabilityandEDAtoolsinelectronicdesignfieldwithversatiletodesignadigitalelectricclock.
Keywork:
DigitalelectricclockVHDLhardwarelanguageEDAtools
一.设计要求:
1.设计一个电子钟能够显示时,分,秒;24小时循环显示。
2.电子钟有校时,校分,清零,保持和整点报时的功能,具体如下:
(1)数字钟最大计时显示23:
59:
59。
(2)在数字钟正常工作时可以对数字钟进行快速校时、校分,即拨动开关K1可以对小时进行校正,拨动开关K2可以对分进行校正。
(3)在数字中正常工作情况下可以对其进行不断地复位,即拨动开关K3可以是时,分,秒显示回零。
(4)在数字钟正常工作时拨动开关K4可以使数字钟保持原有显示,停止计时。
(5)整点报时是要求数字钟在每小时整点到来前进行鸣叫,鸣叫频率是在59:
53,59:
55,59:
57为1kHz,59:
59为2kHz。
3.要求所有开关具有去抖动功能。
利用开发工具QuartusII7.0并结合硬件描述语言VHDL,采用层次化的方法进行设计,要求设计层次清晰,合理;构成整个设计的功能可以采用原理图输入或文本输入法实现。
4.通过开发工具QuartusII7.0对设计电路进行功能仿真。
5.将仿真通过的逻辑电路下载到EDA试验系统,对其功能进行验证。
二.总体方案设计:
从设计要求可以对其进行层次化设计,将所要设计的多功能数字钟分层6个模块:
(1)计时模块:
包括两个模60的计数器(计秒与计分)和一个模24的计数器(计时)。
(2)清零,保持模块:
此模块功能是可以在计时模块直接嵌入即利用计数器的清零、保持功能就可以实现。
(3)校准模块:
其对时、分进行校正。
(4)显示模块:
将数字钟在数码管上显示。
(5)整点报时模块:
由两部分组成,一部分选择报时时间(59:
53,59:
55,59:
57,59:
59),一部分选择报时频率(1kHz,2kHz)。
(6)分频模块:
电子钟的激励源要求的是稳定1Hz,而试验台提供48MHz的时钟,所以要设计一个分频器将48MHz进行分频得到1Hz。
(7)防抖动模块:
因为设计中有使用到开关,而对机械开关而言出现抖动现象会导致系统误差甚至不能正常工作。
所以在设计中要求有去抖动电路。
将数字钟的各功能模块级联,生成顶层电路,实现总体设计要求,设计框图如下图所示:
三.各子模块设计原理:
1.计秒模块:
是一个模60的计数器,具有计时、保持、清零的功能。
采用VHDL硬件语言编写,程序代码如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYsecondIS
PORT(clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
en:
INSTD_LOGIC;
qout1:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
qout2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
co:
OUTSTD_LOGIC);
ENDsecond;
ARCHITECTUREbehavOFsecondIS
SIGNALtem1:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALtem2:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,rst)
BEGIN
IF(en='1')THEN
tem1<=tem1;
tem2<=tem2;
ELSIF(rst='0')THEN
tem1<="0000";
tem2<="0000";
ELSIF(clk'eventANDclk='1')THEN
IFtem1="1001"THEN
tem1<="0000";
IFtem2="0101"THEN
tem2<="0000";
co<='1';
ELSE
tem2<=tem2+1;
co<='0';
ENDIF;
ELSE
tem1<=tem1+1;
ENDIF;
ENDIF;
qout1<=tem1;
qout2<=tem2;
ENDPROCESS;
ENDbehav;
其仿真波形图如下:
封装图为:
2.计分模块:
本质上是跟计秒模块一样,也是模60的计数器,具有计数、保持、清零功能。
程序代码如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYminuteIS
PORT(clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
en:
INSTD_LOGIC;
qout1:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
qout2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
co:
OUTSTD_LOGIC);
ENDminute;
ARCHITECTUREbehavOFminuteIS
SIGNALtem1:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALtem2:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,rst)
BEGIN
IF(en='1')THEN
tem1<=tem1;
tem2<=tem2;
ELSIF(rst='0')THEN
tem1<="0000";
tem2<="0000";
ELSIF(clk'eventANDclk='1')THEN
IFtem1="1001"THEN
tem1<="0000";
IFtem2="0101"THEN
tem2<="0000";
co<='1';
ELSE
tem2<=tem2+1;
co<='0';
ENDIF;
ELSE
tem1<=tem1+1;
ENDIF;
ENDIF;
qout1<=tem1;
qout2<=tem2;
ENDPROCESS;
ENDbehav;
仿真波形图如下:
封装图为:
3.计时模块:
是一个模24的计数器,VHDL的程序代码如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYhourIS
PORT(clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
en:
INSTD_LOGIC;
qout1:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
qout2:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
co:
OUTSTD_LOGIC);
ENDhour;
ARCHITECTUREbehavOFhourIS
SIGNALtem1:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALtem2:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk,rst)
BEGIN
IF(en='1')THEN
tem1<=tem1;
tem2<=tem2;
ELSIF(rst='0')THEN
tem1<="0000";
tem2<="0000";
ELSIF(clk'eventANDclk='1')THEN
IF(tem2="0010"ANDtem1="0011")THEN
tem1<="0000";
tem2<="0000";
co<='1';
ELSE
co<='0';
IF(tem1="1001")THEN
tem1<="0000";
tem2<=tem2+1;
ELSE
tem1<=tem1+1;
ENDIF;
ENDIF;
ENDIF;
qout1<=tem1;
qout2<=tem2;
ENDPROCESS;
ENDbehav;
仿真波形图如下:
封装图为:
4.校准模块:
在正常情况下,分的输入时钟clk信号是由秒的进位输出给的,而时的输入时钟clk信号由分进位输出信号给的。
当要进行校准时可以直接将2Hz的时钟信号(从分频器直接分出来)送到分或时的输入时钟clk端上,这样就可以快速的进行对电子钟的分或时校准。
因此采用VHDL语言实现,程序代码如下:
(1)校时:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYjiaoshiIS
PORT(clk:
INSTD_LOGIC;
clk_2H:
INSTD_LOGIC;
key:
INSTD_LOGIC;
en:
OUTSTD_LOGIC;
co:
OUTSTD_LOGIC
);
ENDjiaoshi;
ARCHITECTUREbehavOFjiaoshiIS
SIGNALtem:
STD_LOGIC;
SIGNALx:
STD_LOGIC;
BEGIN
PROCESS(key)
BEGIN
IF(key='0')THEN
x<='0';
tem<=clk;
ELSE
x<='1';
tem<=clk_2H;
ENDIF;
co<=tem;
en<=x;
ENDPROCESS;
ENDbehav;
其封装图为:
(2)校分:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYjiaofenIS
PORT(clk:
INSTD_LOGIC;
clk_2H:
INSTD_LOGIC;
key:
INSTD_LOGIC;
co:
OUTSTD_LOGIC
);
ENDjiaofen;
ARCHITECTUREbehavOFjiaofenIS
SIGNALtem:
STD_LOGIC;
BEGIN
PROCESS(key)
BEGIN
IF(key='0')THEN
tem<=clk;
ELSE
tem<=clk_2H;
ENDIF;
co<=tem;
ENDPROCESS;
ENDbehav;
其封装图为:
5.显示模块:
采用动态显示方法,其动态扫描频率为1MHz。
显示模块包括一个6选1数据选择器(其从计数模块输出的6个输出选1个送出显示)和一个译码器(其对6选1数据选择器的输出信号进行译码送至数码管上显示)。
用VHDL硬件语言实现即程序代码如下:
(1)6选1数据选择器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYselIS
PORT(clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
qin1:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin2:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin3:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin4:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin5:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin6:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qout:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
sel:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDsel;
ARCHITECTUREbehavOFselIS
BEGIN
PROCESS(clk,rst)
VARIABLEt:
INTEGERRANGE0TO5;
BEGIN
IF(rst='0')THEN
cnt:
=0;
sel<="00000000";
qout<="0000";
ELSIF(clk'eventANDclk='1')THEN
IF(cnt=5)THEN
cnt:
=0;
ELSE
cnt:
=cnt+1;
ENDIF;
CASEtIS
WHEN0=>qout<=qin1;
sel<="11111110";
WHEN1=>qout<=qin2;
sel<="11111101";
WHEN2=>qout<=qin3;
sel<="11111011";
WHEN3=>qout<=qin4;
sel<="11110111";
WHEN4=>qout<=qin5;
sel<="11101111";
WHEN5=>qout<=qin6;
sel<="11011111";
WHENothers=>qout<="0000";
sel<="11111111";
ENDCASE;
ENDIF;
ENDPROCESS;
ENDbehav;
仿真波形:
例如显示23:
15:
39其从仿真波形结果可看知所设计的是正确的。
其封装图为:
(2)4-7译码器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYdecode47IS
PORT(qin:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qout:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDdecode47;
ARCHITECTUREbehavOFdecode47IS
BEGIN
WITHqinSELECT
qout<="00000011"WHEN"0000",
"10011111"WHEN"0001",
"00100101"WHEN"0010",
"00001101"WHEN"0011",
"10011001"WHEN"0100",
"01001001"WHEN"0101",
"01000001"WHEN"0110",
"00011111"WHEN"0111",
"00000001"WHEN"1000",
"00011001"WHEN"1001",
"00000011"WHENOTHERS;
ENDbehav;
其封装图为:
6.报时模块:
由设计要求电子钟在每小时到来前进行报时:
59:
53,55:
55,59:
57鸣叫频率为1kHz;59:
59鸣叫频率为2kHz,从而可以很容易采用VHDL语言编写程序实现,代码如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYbellIS
PORT(clk_1k:
INSTD_LOGIC;
clk_2k:
INSTD_LOGIC;
qin1:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin2:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin3:
INSTD_LOGIC_VECTOR(3DOWNTO0);
qin4:
INSTD_LOGIC_VECTOR(3DOWNTO0);
bel:
OUTSTD_LOGIC
);
END
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