DRAM Guide.docx
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DRAM Guide.docx
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DRAMGuide
PartIDRAMandSRAMBasics
Storagetheory
Attheriskofturningsomereadersoffbystartingoutontooelementaryofalevel,I'llbeginbystatingwhatwealreadyknow:
RAMiswhereyoustorecodeanddatasotheCPUcanworkwithit.Now,beforeyoumorehardcoretypeshitthenextpagelookingforsome"real"info,stopforasecondandthinkwhatthatsimplestatementimpliesaboutthekindsofthingsthatyouneedinordertostorestuff(code,data,boxes,widgets,etc.).Somebasicthinkingaboutthetaskofstoringstuffwillreallyhelpyouunderstandthemoreesotericpartsofatechnologythat'sdesignedwiththestorageofstuffasitsprimarygoal.
Firstoff,ifwe'restoringlotsofsmallthings(andwedefinitelyare),thenwecandividethestoragespaceupintosmallbinsandstickoneitemineachbin.Ofcourse,ifeachitemwe'restoringisunique(anditdefinitelyis)andwe'reevergoingtobeabletoretrieveaspecificitem,weneedanorganizationalschemetoorderthestoragespace.Stickingaunique,numericaladdressoneachbinworks,sothat'swhatwe'lldo.Theaddresseswillstartatsomenumberandincrementbyoneforeachbin.Thus,tous,thestoragespacelookslikeastraightlineofbins,eachwithadifferentaddress.Ifwewantedtosearchtheentirestoragespace,we'dstartwiththelowestaddressanditeratethrougheachsuccessiveoneuntilwegettothehigheraddress.Notethatifwecontractedthestoringofourstuffouttoa3rdparty,that3rdpartycouldlayoutthephysicalstoragespacehowevertheywant--arow,agrid,acube,etc.Allthatmattersiswhenwegivethemaseriesofaddresses,theycangettherightitemoutofeachlocationwithoutuseverhavingtoknowthephysicaldetailsofhowtheitemsarestored.
Now,oncewe'vegotthestoragespaceorganizedproperly,we'llneedawaytogettheitemsintoandoutofit.ForRAMstorage,thedatabusiswhatallowsustomovestuffintoandoutofstorage.Andofcourse,sincethestoragespaceisorganized,weneedawaytotelltheRAMexactlywhichlocationcontainstheexactdatathatweneed;thisisthejoboftheaddressbus.TotheCPU,theRAMlookslikeonelong,thinlineofstoragecells,eachwithauniqueaddress.IftheCPUwantsapieceofdatafromRAM,itfirstplacestheaddressofthelocationontheaddressbus.Itthenwaitsafewcyclesandlistensonthedatabusfortherequestedinformationtoshowup.CheckoutthefollowingconceptualpictureofhowRAMlookstoaCPU.
Thoselittleroundthingsinthemiddlearememorycells,andeachoneishookedintoauniqueaddressline.Theaddressdecodertakestheaddressoffoftheaddressbusandidentifieswhichcelltheaddressisreferringto.Itthenactivatesthatcell,andthedatainitdropsdownintothedatainterfacewhereit'splacedonthedatabusandsentbacktotheCPU.
TheCPUseesthosecellsasarowofaddressablestoragespacesthathold1byteeach,soitunderstandsmemoryasarowofbytes.Unlikewhatthepreviousexampleimplies,however,intherealworldtheCPUnevergrabsdataonebyteatatime.Itusuallygrabsitin32-bitor64-bitchunks,dependingonthewidthofthedatabus.Soifthedatabusis64-bitswideandtheCPUneedsoneparticularbyte,it'llgoaheadandgrabthebyteitneedsalongwiththe7bytesthatarenexttoit.Itgrabs8bytesatatimebecausea)itwantstofilluptheentiredatabuswithdataeverytimeitmakesarequestandb)it'llprobablyendupneedthoseother7bytesshortly.
Notaline,butagrid
JustbecausetheCPUseesRAMasonelong,thinlineofbytesdoesn'tmeanthatit'sactuallylaidoutthatway.Insteadoftryingtodesignandmanufactureachipthat'slongenoughtoaccommodateafewmillionbytesinarow,abetter,lessexpensive(andlessgoofylooking)waytoapproachtheproblemistoorganizethecellsinagridofindividualbitsandsplituptheaddressintorowsandcolumns,whichyoucanusetolocatetheindividualbitthatyouneed.Thisway,ifyouwantedtostore,say,1024bits,youcanusea32x32gridtodoso.Obviously,a32x32gridisamuchmorecompactdesignthanasinglerowof1024bits.Checkit:
Thegridschemeworksprettywell,andisinfactroughlyhowRAMchipsarelaidout.
Inasimple,idealizedsystemliketheoneabovewithonlyoneRAMchip,theCPU,inrequestingandindividualbitwouldplaceanaddressintheformofastringof22binarydigits(forthex86)ontheaddressbus.TheRAMinterfacewouldthenbreakthatstringofnumbersinhalf,anduseonehalfasan11digitrowaddressandonehalfasan11digitcolumnaddress.Therowdecoderwoulddecodetherowaddressandactivatetheproperrowlinesothatallthecellsonthatrowbecomeactive.Thenthecolumndecoderwoulddecodethecolumnaddressandactivatethepropercolumnline,selectingwhichparticularcellontheactiverowisgoingtohaveitsdatasentbackoutoverthedatabusbythedatainterface.Also,notethatthegriddoesnothavetobesquare,andinfactinreallifeit'susuallyarectanglewherethenumberofrowsislessthanthenumberofcolumns.(We'lldiscusswhythatiswhenwetalkaboutDRAM.)
TheaboveschemeroughlyreflectshowabasicSRAMchipworks.SRAMstandsfor"staticRAM,"andit'ssonamedbecauseoncedataisputinacellitjustsitsthereanddoesn'ttrickleout.(AsopposedtoDRAM,wherethedataleaksoutofthecelleveryfewmillisecondsunlessyourefreshit.Moreonthatinamoment,though).AnSRAMcellisusuallymadeupofabout4to6transistors,arrangedinaconfigurationthattrapseitherabinary1orabinary0inbetweenthemuntilthatvalueiseitherwrittenoverwithanewvalueorthepowergoesout.SRAMisveryfastandverypowerefficient,butthefactthatittakes4to6transistorstomakeonememorycell(vs.onetransistorforoneDRAMmemorycell)meansthatit'swayexpensivetoproduce.
RAMChips
Mydiagramsandexplanationssofarhavebeenfairlysimplifiedandabstracted,sonowit'stimetogetabitmoreconcrete.Specifically,nowthatyouunderstandtheverybasics,we'vegottotalkaboutoneofthemostimportantissuesinRAMtechnology:
packaging.You'veprobablyallheardabout30-pinSIMMS,72-pinSIMMS,DIMMS,RIMMs,etc.Thereasontherearesomanyvarietiesofpackagingisthatastransistorsshrinkinsizeandthenumberofcellsyoucancramonagridincreases,you'vegottochangethewayyoupackageandusethechipstotakeadvantageofnewcapabilities.Aswe'llseeinthenextfewsections,RAMisorganizedbygroupingtheindividualgridsdescribedaboveintoevermorenestedandcomplicatedconfigurations.Becauseofthis,I'mgoingtostartoutbybrieflycoveringthemostbasicunitofRAMorganization:
theRAMchip.
SRAMchips
EarlySRAMchipscamein20-pinandlargerDIPs(DualInlinePackages).Theyhadtohavealargenumberofpinsbecausetherehadtobe
∙apinforeachaddresssignal
∙aDataInpinandaDataOutpin
∙somecontrolpins(WriteEnable,ChipSelect)
∙GroundandPowerpins.
Attheriskofmakingyoureyesglazeover,I'mgoingtodroparealSRAMpin-outdescriptiononyourightnow.Fearnot,though,becausethenameandpurposeofeachpinisprettystraightforward,andinfactyou'vealreadymet16ofthe20pinsinthefollowing16Kx1-bitSRAM.
AsidefromVccandGND,thepurposesofwhichshouldbeobvious,theonlypinsintheabovepackagewehaven'tcoveredsofarare/CSand/WE.(Puttinga"/"infrontofthepinnameisthestandardtextwayofwritingitwithalineoverit.The"/"orlinesignifiesthatthepinisactivatedbyalowvoltage,orlogic0,butthatdoesn'treallymatterrightnowforourdiscussion).Let'sbreakthepins'functionsdownonebyone:
∙ChipSelect:
Inarealsystem,therecouldbeanynumberofSRAMchipsattachedtotheaddressanddatabuses,soyouusetheChipSelecttoselecttheparticularSRAMchipthatyouwanttowritetoorreadfrom.
∙WriteEnable:
WhenyougivetheSRAManaddress,you'vegottotellitwhetheryou'regoingtobewritingtoorreadingfromthataddress.The/WEpinletsyoutelltheSRAMthatyouintendtowritetotheaddressyoujustgaveit.
∙OutputEnable:
There'sonestandardpinthat'smissingfromtheaboveSRAM,afactthatmakesexplainingthestepsinitsreadandwritecyclesmorecomplicatedthanitshouldbe.ThatpinistheOutputEnablepin,anditsjobistolettheSRAMknowthatit'sbeingreadfromandnotwrittentoo.SincemostmodernSRAMsdon'thaveitanymoreIcouldn'tforthelifeofmefindadatasheetforax1-bitSRAMthatusesit.Thisbeingthecase,we'lljustpretendthattheaboveSRAMhasan/OEpin,andexplainthingsaccordingly.
Soreading1bitofdatafromtheDataOutpinwouldrequirethefollowingsteps
SRAMRead
1)Placetheaddressofthebittobereadontheaddresspinsviatheaddressbus.(MakesureWriteEnableisnotactivewhenthishappens,sothattheSRAMknowsit'snotbeingwrittento.)
2)ActivateChipSelecttoselecttheSRAMchip.
3)ActivatetheOutputEnablepinsothattheSRAMknowsit'sbeingreadfrom.
Afterthatlaststepiscomplete,thedatayouwantwillappearontheDataOutpinandmoveontothedatabus.Prettysimple,eh?
Thestepsforwriting1bitofdatatotheSRAMarealmostassimple.
SRAMWrite
1)Placetheaddressofthecelltobewrittentoontheaddresspinsviatheaddressbus.(Makesurethe
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