华南理工大学 数字系统设计全英B卷.docx
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华南理工大学 数字系统设计全英B卷.docx
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华南理工大学数字系统设计全英B卷
1.Multiplechoicetest(2ⅹ5=10marks)
1.WhichofthefollowingstatementsonVHDLprocessisnottrue(C)
A.asignalcanbereadinmultipleprocesses;
B.asignalcanbeassignedvaluesformultipletimesinaprocess,however,onlythelastassignmenttakeseffect;
C.asignalcanbeassignedvaluesindifferentprocess;
D.aprocesscanbetriggeredeitherbymeansofsensitivitylistorbywaitstatement;
2.Whichofthefollowingstatementsisnottrue(D)
A.Theworkingfrequencyofasynchronousdigitalsystemshouldn’texceedthereciprocal(倒数)ofitsmaximaldelay;
B.Theworkingfrequencyofasynchronousdigitalsystemislimitedbythedelayofitscomponents.
C.Asynchronousdigitalsystemismoreefficientintermsofresourcesthansynchronoussystem.
D.Asynchronousdigitalsystemismorereliablethansynchronoussystem.
3.Whichofthefollowingstatementsonsynthesisisnottrue(D)
A.Synthesisisatransformationprocessfromonerepresentationofthedesigntoanotherrepresentationform;
B.SynthesistransformsthehighlevelHDLtolowlevelhardwarenetlist,whichisproducedaccordingtoFPGA/CPLDstructure;
C.Synthesisisusuallylimitedbythesurfaceandspeedofthecircuit;
D.Synthesisisamappingprocessfromhighleveldescriptiontolowlevelhardwarerepresentation.Themappingrelationshipisuniqueandthesynthesisresultisunique.
4.WhichofthefollowingstatementsonVHDLsimulation&synthesisisnottrue:
(B)
A.thetimedelayfollowingtheafterstatementcan’tbesynthesized;
B.Apulsesignalcan’tpropagatethroughthepathifitsdurationislessthantransportdelay;
C.ForaVHDLsignal,itsinitialvalueassignedinitsdeclarationpartisvalidinsimulationonly;it’signoredbytheVHDLsynthesis;
D.Simulationisactuallyaprocessofcheckingandverification;
5.Instatemachinecoding,(A)cansavetheresourcesfordecodingandreducetheriskofillegalstatesatthepriceofmoreregisterresources:
A.one-hotcodingB.randomcodingC.naturalbinarycodingD.graycode
2.ShortQ&A(10ⅹ2=20marks)
1、Thefollowingfigureshowsthecriticalpathofadigitalsystem.(10marks)
(1)Pleasegiveabriefexplanationrespectivelyforthetimingparametersincludingtsu,thold,tc-q,tlogic
(2)Accordingthetimingparametersinthefigure,calculatethemaximaldelayτmaxofthecriticalpath(orthemaximalworkingfrequencyfmaxofthesystem).
Setuptime:
Toensurereliableoperation,theinputtoaregistermustbestableforaminimumtimebeforetheclockedge(registersetuptimeortSU).ifthetimeisnotlongenough,reliableoperationcannotbeguaranteed
Holdtime:
Toensurereliableoperation,theinputtoaregistermustbestableforaminimumtimeaftertheclockedge(registerholdtimeortH).ifthetimeisnotlongenough,reliableoperationcannotbeguaranteed.
Tcq
Theregisteroutputthenisavailableafteraspecifiedclock-to-outputdelay(tcoortcq).
tlogic
Theworstcombinationalogicdealy
τmax=tcq+tsu+tlogic
2.PleasedrawtheRTLdiagramsforthefollowing2piecesVHDLcodes(10marks)
(1)
process(op,x,y)
begin
ifop=‘0’then
result<=xory;
else
result<=xandy;
endif;
endprocessP2;
(2)
ENTITYtestIS
PORT(X,Y:
instd_logic;
Sum,Carry:
outstd_logic);
ENDtest;
ARCHITECTUREdataflowOFtestIS
BEGIN
Sum<=XxorY;
Carry<=XandY;
ENDdataflow;
3.Comprehension&Design(60marks)
1、Designa4-1MuxusingsynthesizableVHDLstatements(10marks)
Selectionsignals:
S0、S1;
Datainput:
A、B、C、D;
Dataoutput:
Dout。
LIBRARYIEEE;
USEIEEE.std_logic_1164.ALL;
EntityMux41is
Port(s0,s1,A,B,C,D:
instd_logic;
Dout:
outstd_logic);
Endentity;
ArchitecturebehaviorofMux41is
Signalsel:
std_logic_vector(1downto0);
begin
sel<=s0&s1;
process(sel,A,B,C,D)
begin
caseselis
when"00"=>Dout<=A;
when"01"=>Dout<=B;
when"10"=>Dout<=C;
when"11"=>Dout<=D;
whenothers=>Null;
endcase;
endprocess;
endarchitecture;
2、UsingVHDL,describethe2stimulishownbythefollowingdiagram,asaparttestbench。
(6marks)
…
SignalS1:
std_logic;
SignalS2:
std_logic;
…
Process
Begin
S1<=’0’;
Waitfor10ns;
S1<=’1’;
Waitfor5ns;
S1<=’0’;
Waitfor10ns;
Endprocess;
Process
Begin
S1<=’0’;
Waitfor5ns;
S1<=’1’;
Waitfor15ns;
S1<=’0’;
Waitfor5ns;
Endprocess;
3.ModelthefollowingcircuitusingVHDLaccordingtothefollowingrequirements:
(8marks)
(a)TAandTBareenablesignals,bothofthemareinactive(无效),Yissettohighimpedance;
(b)ifbothofTAandTBareactive(有效),Yfollowsthewired-andlogic(线与逻辑)of‘AandB’;
(c)ifonlyTA(orTB)isactive,YfollowsinputA(orinputB);
LIBRARYIEEE;
USEIEEE.std_logic_1164.ALL;
LIBRARYIEEE;
USEIEEE.std_logic_1164.ALL;
Entitytestis
Port(TA,TB,A,B:
instd_logic;
Y:
outstd_logic);
Endentity;
Architecturebehavioroftestis
Signalsel:
std_logic_vector(1downto0);
begin
sel<=TA&TB;
process(sel,A,B)
begin
caseselis
when"00"=>Y<='Z';
when"01"=>Y<=B;
when"10"=>Y<=A;
when"11"=>Y<=AandB;
whenothers=>Null;
endcase;
endprocess;
endarchitecture;
4、readthefollowingVHDLcodes,andexplainitsfunction(6marks)
Libraryieee;
Useieee.std_logic_1164.all;
entity s4 is
port (clk, rst :
in std_logic;
load,en :
in std_logic;
din :
in STD_LOGIC_VECTOR (7 downto 0);
qb :
out std_logic);
end s4;
architecture behav of s4 is
signal reg8:
std_logic_vector( 7 downto 0);
begin
process (clk, RST , load, en)
begin
if rst='1' then
reg8 <= (OTHERS=>'0') ;
elsif CLK'EVENT AND CLK='1' then
if load = '1' then
reg8 <= din;
elsif en='1' then
reg8(6 downto 0) <= reg8(7 downto 1) ;
end if;
end if
end process
qb<=_reg8(0);
endbehav;
Thevhdlcodesdescribedaright-shiftregisterwithasynchronousresetinput,synchronousloadinputandsynchronousenablesignal.
5、Designaup-counterbasedonBCDcode(基于BCD码的递增计数器),whichhasthefollowingrequirements:
(10marks)
(a)Load:
Synchronousloadingcontrolsignal;
(b)Data:
BCDcodeddatainput.If‘Load’ishigh,itisloadedintothecounterastheinitialstateofcounting;
(c)Co:
carry_outbit,ifthecountervaluereaches10(decimal),thecounterreturnsto0(decimal),andCoissetto‘1’.
LIBRARYIEEE;
USEIEEE.std_logic_1164.ALL;
UseIEEE.std_logic_unsigned.all;
Entitytestis
Port(load,clk:
instd_logic;
data:
instd_logic_vector(3downto0);
Co:
outstd_logic);
Endentity;
Architecturebehavioroftestis
Signalcount:
std_logic_vector(3downto0);
Begin
Process(clk)
begin
Ifclk'eventandclk='1'then
Ifload='1'then
Count<=data;
Else
Ifcount="1001"then
Count<="0000";
Co<='1';
else
Count<=count+1;
Co<='0';
Endif;
Endif;
endif;
endprocess;
endarchitecture;
6.Solveoneofthefollowingtwoproblems:
(5marks)
(1)drawthewaveformsaccordingtothefollowingVHDLcodes.Attention:
theinitialvalueofsignal‘a’is‘0’,theprocessexecutiondelayisassumedtobedelta
signala:
std_logic:
=‘0’;
……..
process(a)
begin
a<=‘1’;
if(a=‘1’)then
a<=transport‘0’after20ns;
else
a<=transport‘1’after10ns;
endif;
endprocess;
(2)Inadigitalsystem,itsinertialdelayisassumedtobe4ns,thetransportdelayis3ns.ThewaveformofsignalXisshowninthefollowingfigure,pleasedrawthewaveformofZ1,Z2.
Z1<=X;
Z2<=transportXafter3ns;
7.Wehave4piecesofVHDLcodes,pleasechoose3pieces,anddrawtheircorrespondingRTLdiagrams.(15marks)
(a)
ARCHITECTUREBEHAVOFtest1IS
BEGIN
PROCESS(clk)
variablerega,regb:
std_logic;
BEGIN
ifclk='1'andclk'eventTHEN
rega:
=data;
regb:
=rega;
ENDIF;
y<=regb;
ENDPROCESS;
endbehav;
(b)
ARCHITECTUREBEHAVOFtest1IS
BEGIN
PROCESS(clk)
variablerega,regb:
std_logic;
BEGIN
ifclk='1'andclk'eventTHEN
regb:
=rega;
rega:
=data;
ENDIF;
y<=regb;
ENDPROCESS;
endbehav;
(c)
ARCHITECTUREBEHAVOFtest3IS
signalrega,regb:
std_logic;
BEGIN
PROCESS(clk)
BEGIN
ifclk='1'andclk'eventTHEN
regb<=rega;
rega<=data;
ENDIF;
y<=regb;
ENDPROCESS;
endbehav;
(d)
ARCHITECTUREBEHAVOFtest1IS
BEGIN
PROCESS(clk)
variablerega:
std_logic;
BEGIN
ifclk='1'andclk'eventTHEN
rega:
=data;
ENDIF;
y<=rega;
ENDPROCESS;
endbehav;
a
b
c
d
8.UsingVHDL,designacircuitforcountingtheleadingzerosofvectors.Eachvectorincludes8bits,ThevectorsareinputintothecounterinserialorderfromLSBtoMSB(由低位到高位串行输入).
(1)DrawtheASMchartorthestatetransitiondiagramforthecircuit.(5marks)
(2)BasedontheASMchartorstatetransitiondiagram,describethecircuitusingVHDLcode(5marks)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYleading_zerosIS
PORT(clock,data,start:
INstd_logic;
number:
OUTstd_logic_vector(3downto0));
ENDENTITYleading_zeros;
ARCHITECTUREasm3OFleading_zerosIS
TYPEstate_typeIS(s0,s1,s2,s3,s4,s5,s6,s7);
SIGNALpr_state,next_state:
state_type;
BEGIN
seq:
PROCESS(clock,start)
BEGIN
IFstart='1'THEN
pr_state<=s0;
ELSIF(rising_edge(clock))THEN
pr_state<=next_state;
ENDIF;
ENDPROCESSseq;
ns:
PROCESS(pr_state)
BEGIN
CASEpr_stateIS
WHENs0=>next_state<=s1;
WHENs1=>next_state<=s2;
WHENs2=>next_state<=s3;
WHENs3=>next_state<=s4;
WHENs4=>next_state<=s5;
WHENs5=>next_state<=s6;
WHENs6=>next_state<=s7;
WHENs7=>next_state<
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