VHDL流水线加法器.docx
- 文档编号:11096541
- 上传时间:2023-02-25
- 格式:DOCX
- 页数:23
- 大小:1.09MB
VHDL流水线加法器.docx
《VHDL流水线加法器.docx》由会员分享,可在线阅读,更多相关《VHDL流水线加法器.docx(23页珍藏版)》请在冰豆网上搜索。
VHDL流水线加法器
可编程实验报告
实验报告要求:
1、任务的简单描述
2、画出电路图
3、写出源代码
4、仿真结果
5、分析和讨论
1、3-8译码器
源代码:
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_signed.all;
ENTITYdc38IS
PORT(
sel:
instd_logic_vector(2downto0);
y:
outstd_logic_vector(7downto0));
ENDdc38;
ARCHITECTUREbehaviorOFdc38IS
BEGIN
y<="11111110"WHENsel="000"else
"11111101"WHENsel="001"else
"11111011"WHENsel="010"else
"11110111"WHENsel="011"else
"11101111"WHENsel="100"else
"11011111"WHENsel="101"else
"10111111"WHENsel="110"else
"01111111"WHENsel="111"else
"ZZZZZZZZ";
ENDbehavior;
仿真结果:
一位全加器
A
B
CI
S
CO
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
四级流水加法器
一位全加器
第一级锁存器
第三级锁存器
一位全加器
第二级锁存器
一位全加器
第四级锁存器
一位全加器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityadderis
port(
clk,rst:
instd_logic;
a,b:
instd_logic_vector(3downto0);
sum:
outstd_logic_vector(3downto0);
c:
outstd_logic);
endentityadder;
architecturedepictofadderis
signalreg1:
std_logic_vector(7downto0);
signalreg2:
std_logic_vector(6downto0);
signalreg3:
std_logic_vector(5downto0);
begin
bit0:
process(clk,rst)
begin
if(rst='1')then
reg1<="00000000";
elsif(rising_edge(clk))then
reg1(0)<=a(0)xorb(0);
reg1
(1)<=a(0)andb(0);
reg1
(2)<=a
(1);
reg1(3)<=b
(1);
reg1(4)<=a
(2);
reg1(5)<=b
(2);
reg1(6)<=a(3);
reg1(7)<=b(3);
endif;
endprocessbit0;
bit1:
process(clk,rst)
begin
if(rst='1')then
reg2<="0000000";
elsif(rising_edge(clk))then
reg2(0)<=reg1(0);
reg2
(1)<=reg1
(1)xorreg1
(2)xorreg1(3);
reg2
(2)<=(reg1
(1)andreg1
(2))or(reg1
(1)andreg1(3))or(reg1
(2)andreg1(3));
reg2(6downto3)<=reg1(7downto4);
endif;
endprocessbit1;
bit2:
process(clk,rst)
begin
if(rst='1')then
reg3<="000000";
elsif(rising_edge(clk))then
reg3(1downto0)<=reg2(1downto0);
reg3
(2)<=reg2
(2)xorreg2(3)xorreg2(4);
reg3(3)<=(reg2
(2)andreg2(3))or(reg2
(2)andreg2(4))or(reg2(3)andreg2(4));
reg3(5downto4)<=reg2(6downto5);
endif;
endprocessbit2;
bit3:
process(clk,rst)
begin
if(rst='1')then
sum<="0000";
c<='0';
elsif(rising_edge(clk))then
sum(2downto0)<=reg3(2downto0);
sum(3)<=reg3(3)xorreg3(4)xorreg3(5);
c<=(reg3(3)andreg3(4))or(reg3(3)andreg3(5))or(reg3(4)andreg3(5));
endif;
endprocessbit3;
enddepict;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitynoaddis
port(
clk,rst:
instd_logic;
a,b:
instd_logic_vector(3downto0);
sum:
outstd_logic_vector(3downto0);
c:
outstd_logic);
endentitynoadd;
architecturedepictofnoaddis
signalreg:
std_logic_vector(4downto0);
signalrega:
std_logic_vector(4downto0);
signalregb:
std_logic_vector(4downto0);
begin
process(clk)
begin
if(rising_edge(clk))then
rega<='0'&a;
regb<='0'&b;
endif;
endprocess;
process(clk)
begin
if(rst='1')then
reg<="00000";
elsif(rising_edge(clk))then
reg<=rega+regb;
endif;
endprocess;
sum<=reg(3downto0);
c<=reg(4);
enddepict;
4位十进制数计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitydec_dispisport(
clk_cnt:
instd_logic;
sel1:
outstd_logic_vector(3downto0);
sel2:
outstd_logic_vector(3downto0);
sel3:
outstd_logic_vector(3downto0);
sel4:
outstd_logic_vector(3downto0));
enddec_disp;
architecturebehavofdec_dispis
signaldata1:
std_logic_vector(3downto0);
signaldata2:
std_logic_vector(3downto0);
signaldata3:
std_logic_vector(3downto0);
signaldata4:
std_logic_vector(3downto0);
begin
count:
process(clk_cnt)
begin
if(rising_edge(clk_cnt))then
if(data1="1001")then
data1<="0000";
else
if(data2="1001")then
data2<="0000";
data1<=data1+1;
else
if(data3="1001")then
data3<="0000";
data2<=data2+1;
else
if(data4="1001")then
data4<="0000";
data3<=data3+1;
else
data4<=data4+1;
endif;
endif;
endif;
endif;
endif;
endprocesscount;
sel1<=data1;
sel2<=data2;
sel3<=data3;
sel4<=data4;
endbehav;
正弦波发生器
sin.mif文件
depth=256;
width=8;
address_radix=dec;
data_radix=dec;
content
begin
0:
131;
1:
134;
2:
137;
3:
141;
4:
144;
5:
147;
6:
150;
7:
153;
8:
156;
9:
159;
10:
162;
11:
165;
12:
168;
13:
171;
14:
174;
15:
177;
16:
180;
17:
183;
18:
186;
19:
188;
20:
191;
21:
194;
22:
196;
23:
199;
24:
202;
25:
204;
26:
207;
27:
209;
28:
212;
29:
214;
30:
216;
31!
219;
32:
221;
33:
223;
34:
225;
35:
227;
36:
229;
37:
231;
38:
233;
39:
234;
40:
236;
41:
238;
42:
239;
43:
241;
44:
242;
45:
244;
46:
245;
47:
246;
48:
247;
49:
249;
50:
250;
51:
250;
52:
251;
53:
252;
54:
253;
55:
254;
56:
254;
57:
255;
58:
255;
59:
255;
60:
255;
61:
255;
62:
255;
63:
255;
64:
255;
65:
255;
66:
255;
67:
255;
68:
255;
69:
255;
70:
254;
71:
254;
72:
253;
73:
252;
74:
251;
75:
250;
76:
250;
77:
249;
78:
247;
79:
246;
80:
245;
81:
244;
82:
242;
83:
241;
84:
239;
85:
238;
86:
236;
87:
234;
88:
233;
89:
231;
90:
229;
91:
227;
92:
225;
93:
223;
94:
221;
95:
219;
96:
216;
97:
214;
98:
212;
99:
209;
100:
207;
101:
204;
102:
202;
103:
199;
104:
196;
105:
194;
106:
191;
107:
188;
108:
186;
109:
183;
110:
180;
111:
177;
112:
174;
113:
171;
114:
168;
115:
165;
116:
162;
117:
159;
118:
156;
119:
153;
120:
150;
121:
147;
122:
144;
123:
141;
124:
137;
125:
134;
126:
131;
127:
128;
128:
125;
129:
122;
130:
119;
131:
115;
132:
112;
133:
109;
134:
106;
135:
103;
136:
10;
137:
97;
138:
94;
139:
91;
140:
88;
141:
85;
142:
82;
143:
79;
144:
76;
145:
73;
146:
70;
147:
68;
148:
65;
149:
62;
150:
60;
151:
57;
152:
54;
153:
52;
154:
49;
155:
47;
156:
44;
157:
42;
158:
40;
159:
37;
160:
35;
161:
33;
162:
31;
163:
29;
164:
27;
165:
25;
166:
23;
167:
22;
168:
20;
169:
18;
170:
17;
171:
15;
172:
14;
173:
12;
174:
11;
175:
10;
176:
9;
177:
7;
178:
6;
179:
6;
180:
5;
181:
4;
182:
3;
183:
2;
184:
2;
185:
1;
186:
1;
187:
1;
188:
0;
189:
0;
190:
0;
191:
0;
192:
0;
193:
0;
194:
0;
195:
1;
196:
1;
197:
1;
198:
2;
199:
2;
200:
3;
201:
4;
202:
5;
203:
6;
204:
6;
205:
7;
206:
9;
207:
10;
208:
11;
209:
12;
210:
14;
211:
15;
212:
17;
213:
18;
214:
20;
215:
22;
216:
23;
217:
25;
218:
27;
219:
29;
220:
31;
221:
33;
222:
35;
223:
37;
224:
40;
225:
42;
226:
44;
227:
47;
228:
49;
229:
52;
230:
54;
231:
57;
232:
60;
233:
62;
234:
65;
235:
68;
236:
70;
237:
73;
238:
76;
239:
79;
240:
82;
241:
85;
242:
88;
243:
91;
244:
94;
245:
97;
246:
100;
247:
103;
248:
106;
249:
109;
250:
112;
251:
115;
252:
119;
253:
122;
254:
125;
255:
128;
end;
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- VHDL 流水线 加法器