单片机89C52中英文对照翻译经典版.docx
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单片机89C52中英文对照翻译经典版.docx
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单片机89C52中英文对照翻译经典版
单片机89C52中英文对照翻译(经典版)
LT
programmingandverification.
Port3
Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52,asshowninthefollowingtable.Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.
RST
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ThispindrivesHighfor96oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(address8EH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.
ALE/PROG
AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.Innormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
PSEN
ProgramStoreEnable(PSEN)isthereadstrobetoexternalprogrammemory.WhentheAT89S52isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.
EA/VPP
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
XTAL1
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTAL2
Outputfromtheinvertingoscillatoramplifier.
SpecialFunctionRegisters
Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable1.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.
Timer2Registers:
ControlandstatusbitsarecontainedinregistersT2CON(showninTable2)andT2MOD(showninTable3)forTimer2.Theregisterpair(RCAP2H,RCAP2L)aretheCapture/ReloadregistersforTimer2in16-bitcapturemodeor16-bitauto-reloadmode.
InterruptRegisters:
TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthesixinterruptsourcesintheIPregister.
MemoryOrganization
MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.
ProgramMemory
IftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S52,ifEAisconnectedtoVCC,programfetchestoaddresses0000Hthrough1FFFHaredirectedtointernalmemoryandfetchestoaddresses2000HthroughFFFFHaretoexternalmemory.
DataMemory
TheAT89S52implements256bytesofon-chipRAM.Theupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thismeansthattheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccessoftheSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H(whichisP2).MOV0A0H,#data
Instructionsthatuseindirectaddressingaccesstheupper128bytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanP2(whoseaddressis0A0H).
MOV@R0,#data
Notethatstackoperationsareexamplesofindirectaddressing,sotheupper128bytesofdataRAMareavailableasstackspace.
WatchdogTimer
(One-timeEnabledwithReset-out)
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa13-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite
01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.
UsingtheWDT
ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The13-bitcounteroverflowswhenitreaches8191(1FFFH),andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery8191machinecycles.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawrite-onlyregister.TheWDTcountercannotbereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRSTpin.TheRESETpulsedurationis96xTOSC,whereTOSC=1/FOSC.TomakethebestuseoftheWDT,itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset.
WDTDuringPower-downandIdle
InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:
byahardwareresetorviaalevel-activatedexternalinterruptwhichisenabledpriorto
enteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheAT89S52isreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuesto
countifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheAT89S52whileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.
UART
TheUARTintheAT89S52operatesthesamewayastheUARTintheAT89C51andAT89C52.ForfurtherinformationontheUARToperation,refertotheATMELWebsite().Fromthehomepage,select‘Products’,then‘8051-ArchitectureFlashMicrocontroller’,then‘ProductOverview’.
Timer0and1
Timer0andTimer1intheAT89S52operatethesamewayasTimer0andTimer1intheAT89C51andAT89C52.Forfurtherinformationonthetimers’operation,refertotheATMELWebsite().Fromthehomepage,select‘Products’,then‘8051-ArchitectureFlashMicrocontroller’,then‘ProductOverview’.
Timer2
Timer2isa16-bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/T2intheSFRT2CON(showninTable2).Timer2hasthreeoperatingmodes:
capture,auto-reload(upordowncounting),andbaudrategenerator.ThemodesareselectedbybitsinT2CON,asshowninTable3.Timer2consistsoftwo8-bitregisters,TH2andTL2.IntheTimerfunction,theTL2registerisincrementedeverymachinecycle.Sinceamachinecycleconsistsof12oscillatorperiods,thecountrateis1/12oftheoscillatorfrequency.
IntheCounterfunction,theregisterisincrementedinresponsetoa1-to-0transitionatitscorrespondingexternalinputpin,T2.Inthisfunction,theexternalinputissampledduringS5P2ofeverymachinecycle.Whenthesamplesshowahighinonecycleandalowinthenextcycle,the
countisincremented.ThenewcountvalueappearsintheregisterduringS3P1ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles(24oscillatorperiods)arer
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