时序课堂测试参考解答.docx
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时序课堂测试参考解答.docx
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时序课堂测试参考解答
Digitaldesign:
testinclass2(2009)
Name:
Serialnumberinuniversity:
Serialnumberinclass:
Note:
Pleasefinishallyourworksonthetestsheets.
1Filltheblanks(1pointforeach)30point
1-1(29.75)10=(11101.11)2=(35.6)8=(1E.D)16
1-2(10010011)Two’s=(10010010)Ones’=(11101101)SM
1-3(10010011)8421=(11000110)Execess3=(11110011)2421
1-4TheunusedinputportforNORgateshouldbeconnectedto
(Ground,0,anusedport)
1-5Writetheoutputfunctionforthefollowinglogiccircuit:
f1=(ab(c+d));f2=(ab+ac’+bc’)
1-6ThenumbersoftransistorfortheAND3gateshouldbe(8),fortheNOR3gateshouldbe(6),fortheSRlatchshouldbe(8),andfortheDlatchshouldbe(10).
1-7Givenafunction
themaxtermlistofitsdualityshouldbe(
),themintermlistofitscomplementshouldbe(
).
1-8ThecharacteristicequationfortheDflip-flopis(Q*=D),andfortheJKflip-flopis(Q*=JQ’+K’Q).
1-9Some8-bitdatawithoddparitycheckingbitarelistedasfollows,pleaseselectthewrongdata:
(110111010).
001011011011101001110100110110111010
1-10Theminimalnumberofstateoutputforamode60countershouldbe(6).
1-11(3)DFFswillneedtomakeageneratorforaperiodicsequence11101000.
1-12IfuseaJKflip-floptogetthetransitionequation
itsexcitationequationshouldbe(J=K=1);ifuseDFF,thenitsexcitationequationshouldbe(D=Q’).
1-13Thenumberofstatevariablesshouldbeatleast(
)fordescribingnindependentstatesinasequentialdesign.
1-142Mx4bitROMwillhave(21)addressinputportsand(4)dataoutputports。
1-15Thewidthofaddresscodefora512K8EPROMshouldbe(19).
1-16InabasicCMOSgate,ifallofthePMOStransistorsareconnectedinseries,thegateshouldbe(NORgate).
1-17Theresolvingabilityfora12bitADCshouldbe(Vmax/212)
2Judgethestatement:
true(T)orfault(F)(1pointforeach)
2-1Thelatchstorethedatarelyonfeedbackcircle.(T).
2-2TheoutputofaMooremachinemaybechangedwhenitsinputorstatechanged.(F).
2-3Theoutputofasynchronizedevicecanonlybechangedatthepositiveedgeoftheclocksignal.(F).
2-4Thevariableforatransition/outputtableshouldbetransitionsignalandoutputsignal(F).
2-5IfwedesignaFSMwithminimalriskway,weshouldmakethetransitionstateforanyinvalidstatetobeavalidstate.(T).
2-6TheADCwithparallelcomparetechniquewillbemuchfasterthantheADCwithfeedbackandcomparetechnique.(T).
2-7TheriskofmetastableforaSRlatchismuchlesscomparedwithaDlatch.(F).
2-8TheSRAMneedmuchlargerareaonthechipthantheDRAMinsamecapacitance.(T).
2-9Makeamode20binarycounterneed5DFF,butmakeamode20Johnsoncounterneed10DFF.(T).
2-10ForacertainFSMdesign,theindependentstatesofaMooremachinewillbelessthanaMealymachine.(F).
3LogiccircuitAnalyze(5pointforeach)
3-1giventhecircuitasfollows,pleasewriteitslogicequationinmintermlist,anddeterminethestatichazardanditsconditioninthiscircuit.
Solution:
Thestatic1hazardmaybehappenedwhenbc=10ac=01abd=101abd=100.
3-2TheS-Rlatchcircuitisgivenasfollows,iftheinitialstateis0,andtheinputischangedasinthetimediagram,pleasefinishthetimediagramforthestateQ.AssumethetimedelayforeachNAND2is5ns.
Solution:
3-3AFSMisgivenasfollows,pleasewritetheexcitationequationsforeachflip-flop,andgetitstransition/outputtable.
Solution:
Excitationequations:
Transitionequations:
Outputequation:
3-4WritethefeedbackequationsDforthefollowingcircuit,andwriteitstransitiontablewhenload=0.
74194functiontable:
input
Nextstates
function
S1S0
QA*
QB*
QC*
QD*
hold
00
QA
QB
QC
QD
Rightshift
01
SRSI
QA
QB
QC
Leftshift
10
QB
QC
QD
SLSI
Parallel-in
11
A
B
C
D
Solution:
Feedbackequation:
Whenload=1,thestateisset:
Whenload=0,thecircuitisinrightshiftmode,itstransitiontableis:
3-5Writethestatediagramforthefollowingcircuit.
Solution:
3-6ThememoryarrayofaROMissetasfollows,pleasewritetheminimalsumforeachoutputYi.
Solution:
4Logicdesign(6pointforeach)
4-1Designacombinationalcircuitwith4inputs(S2,S1,A,B)and1outputY.Itsfunctiontableisasfollows.Pleasewriteitsoutputequationanduseone74151andoneinvertertorealizeit,writealltheinputequationsforDi’s,andplotthelogicdiagram.(Hint:
connectS2S1AtotheinputportsCBA)
Solution:
Comparewiththestandardoutputof74151:
Wecanget:
4-2Designamealymachineasasignaldetector,oncethe“11010”ishappenedasinputsequence,theoutputshouldbe1andthemachineshouldbebacktoitsinitialstate.Plotitsstatediagram,writeitstransition/outputtablewithbinarycode,andgetitsexcitationequationsforDflip-flopwithminimalcost.
Solution:
4-3Designamode12counterwithGraycodestateassignment.Writeitstransitiontable,andgetitsexcitationequationsforJKflip-flopwithminimalrisk.
Solution:
4-4Designthefeedbacklogicinfollowingcircuit,sothatitwillworkasaperiodicsequencegeneratorfor“110010”.Writeitstransitiontable,getthefeedbacklogicinminimalsum,andplotitsstatediagram.
Solution:
4-5MakeanMSIdesignfortheperiodicsequencegeneratorfor“110010”withonlyone74163andone74151.Pleasewritethevalidstatesforthe74163,andplotthelogicdiagramforthecircuit.
Solution:
Thevalidstatesare:
0000,1011,1100,1101,1110,1111;
Thedatainputsfor74151are:
(D0…D7)=(10010010);
Thelogicdiagramis:
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