EDA程序终极汇总修订后.docx
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EDA程序终极汇总修订后.docx
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EDA程序终极汇总修订后
1.组合逻辑电路:
(1)半加器与全加器(原理图以及VHDL语言)
A.半加器
输入:
2个二进制1位
输出:
和输出S,进位Co
真值表:
A
B
S
Co
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYHALFADDIS
PORT(
A,B:
INSTD_LOGIC;
S,Co:
OUTSTD_LOGIC
);
ENDHALFADD;
ARCHITECTURERTLOFHALFADDIS
BEGIN
S<=AXORB;
Co<=AANDB;
ENDRTL;
原理图:
B.全加器
输入:
2个二进制1位,一个进位输入Ci
输出:
和输出S,进位Co
真值表:
A
B
Ci
S
Co
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFULLADDIS
PORT(
A,B,Ci:
INSTD_LOGIC;
S,Co:
OUTSTD_LOGIC
);
ENDFULLADD;
ARCHITECTURERTLOFFULLADDIS
COMPONENTHALFADD
PORT(A:
INSTD_LOGIC;
B:
INSTD_LOGIC;
S:
OUTSTD_LOGIC;
Co:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALT1,T2,T3:
STD_LOGIC;
BEGIN
U1:
HALFADDPORTMAP(A=>A,B=>B,S=>T1,CO=>T2);
U2:
HALFADDPORTMAP(A=>CI,B=>T1,S=>S,CO=>T3);
Co<=T2ORT3;
ENDRTL;
原理图:
A.分层开发
B.单层开发(课本P114)
(2)全减器(原理图以及VHDL语言)
输入:
2个二进制1位,一个借位输入Ci
输出:
差输出S,借位Co
真值表:
A
B
Ci
S
Co
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFULL_SUBBIS
PORT(
A,B,CI:
INSTD_LOGIC;
S,CO:
OUTSTD_LOGIC
);
ENDFULL_SUBB;
ARCHITECTURERTLOFFULL_SUBBIS
SIGNALNA:
STD_LOGIC;
BEGIN
NA<=NOTA;
S<=AXORBXORCI;
CO<=(NAANDCI)OR(BANDCI)OR(NAANDB);
ENDRTL;
原理图:
(3)译码器
(以下程序均非译码器程序,具体译码器程序可参照数字钟4-7译码器程序)
A.2-4译码器
输入端口:
2个二进制输入端a、b
输入端口:
1个使能控制信号en
输出端口:
4个译码输出端y0—y3
真值表:
输入
输出
EN
A
B
Y3
Y2
Y1
Y0
0
×
×
Z
Z
Z
Z
1
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
1
1
0
0
0
程序:
(程序为四选一选择器,真值表及原理图为2-4译码器)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX4IS
PORT(
Y0,Y1,Y2,Y3,A,B,EN:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
);
ENDMUX4;
ARCHITECTURERTLOFMUX4IS
SIGNALSEL:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
SEL<=A&B;
PROCESS(SEL)
BEGIN
IFEN='0'THEN
Q<='Z';
ELSE
IFSEL="00"THENQ<=Y0;
ELSIFSEL="01"THENQ<=Y1;
ELSIFSEL="10"THENQ<=Y2;
ELSIFSEL="11"THENQ<=Y3;
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
原理图:
B.3-8译码器(程序为八选一选择器,真值表及原理图为3-8译码器)
输入端口:
3个二进制输入端T0,T1,T2
输入端口:
1个使能控制信号EN
输出端口:
4个译码输出端A0—A7
真值表:
输入
输出
EN
T2
T1
T0
A7
A6
A5
A4
A3
A2
A1
A0
0
×
×
×
Z
Z
Z
Z
Z
Z
Z
Z
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX8IS
PORT(
A0,A1,A2,A3,A4,A5,A6,A7:
INSTD_LOGIC_VECTOR(7DOWNTO0);
T0,T1,T2,EN:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDMUX8;
ARCHITECTURERTLOFMUX8IS
SIGNALSEL:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
SEL<=T2&T1&T0;
PROCESS(SEL)
BEGIN
IFEN='0'THEN
Y<="ZZZZZZZZ";
ELSE
IFSEL="000"THENY<=A0;
ELSIFSEL="001"THENY<=A1;
ELSIFSEL="010"THENY<=A2;
ELSIFSEL="011"THENY<=A3;
ELSIFSEL="100"THENY<=A4;
ELSIFSEL="101"THENY<=A5;
ELSIFSEL="110"THENY<=A6;
ELSIFSEL="111"THENY<=A7;
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
(4)编码器
A.优先编码器(8-3)
真值表:
输入
输出
S
D0
D1
D2
D3
D4
D5
D6
D7
Q2
Q1
Q0
Gs
E0
1
×
×
×
×
×
×
×
×
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
×
×
×
×
×
×
×
0
0
0
0
0
1
0
×
×
×
×
×
×
0
1
0
0
1
0
1
0
×
×
×
×
×
0
1
1
0
1
0
0
1
0
×
×
×
×
0
1
1
1
0
1
1
0
1
0
×
×
×
0
1
1
1
1
1
0
0
0
1
0
×
×
0
1
1
1
1
1
1
0
1
0
1
0
×
0
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
程序:
(真值表为优先编码器真值表,程序为普通编码器程序)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYi_encoderIS
PORT(
D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
S:
INSTD_LOGIC;
Gs,E0:
OUTSTD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR(2DOWNTO0)
);
ENDi_encoder;
ARCHITECTURERTLOFi_encoderIS
BEGIN
PROCESS(S,D)
BEGIN
IF(S='1')THEN
q<="111";Gs<='1';E0<='1';
ELSIF(S='0')THEN
IF(d="11111111")THEN
q<="111";Gs<='1';E0<='0';
ELSIF(d(7)='0')THEN
q<="000";Gs<='0';E0<='1';
ELSIF(d(6)='0')THEN
q<="001";Gs<='0';E0<='1';
ELSIF(d(5)='0')THEN
q<="010";Gs<='0';E0<='1';
ELSIF(d(4)='0')THEN
q<="011";Gs<='0';E0<='1';
ELSIF(d(3)='0')THEN
q<="100";Gs<='0';E0<='1';
ELSIF(d
(2)='0')THEN
q<="101";Gs<='0';E0<='1';
ELSIF(d
(1)='0')THEN
q<="110";Gs<='0';e0<='1';
ELSIF(d
(1)='0')THEN
q<="111";Gs<='0';e0<='1';
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
B.普通编码器(4-2)
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYENCODE42IS
PORT(
EN:
INSTD_LOGIC;
I:
INSTD_LOGIC_VECTOR(3DOWNTO0);
A,B:
OUTSTD_LOGIC);
ENDENCODE42;
ARCHITECTURERTLOFENCODE42IS
BEGIN
PROCESS(EN,I)
BEGIN
IF(EN='0')THENA<='0';B<='0';
ELSEIF(I(0)='0')THENA<='0';B<='0';
ELSIF(I
(1)='0')THENA<='0';B<='1';
ELSIF(I
(2)='0')THENA<='1';B<='0';
ELSIF(I(3)='0')THENA<='1';B<='1';
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
(5)四选一选择器
输入端:
4路输入,2bit选择信号,
输出端:
1路输出
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCHOSEIS
PORT(
S:
INSTD_LOGIC_VECTOR(1DOWNTO0);
A,B,C,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
);
ENDCHOSE;
ARCHITECTURERTLOFCHOSEIS
BEGIN
PROCESS(S,A,B,C,D)
BEGIN
CASESIS
WHEN"00"=>Q<=A;
WHEN"01"=>Q<=B;
WHEN"10"=>Q<=C;
WHEN"11"=>Q<=D;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDRTL;
(6)三态门(原理图以及VHDL语言)
数据输入din,控制输入en
数据输出dout
真值表:
数据输入
控制输入
数据输出
X
0
Z
0
1
0
1
1
1
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYTAI3IS
PORT(
DIN,EN:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC
);
ENDTAI3;
ARCHITECTURERTLOFTAI3IS
BEGIN
PROCESS(DIN,EN)
BEGIN
IFEN='1'THEN
DOUT<=DIN;
ELSE
DOUT<='Z';
ENDIF;
ENDPROCESS;
ENDRTL;
状态图:
(7)单向总线缓冲器
输入:
A_IN,使能端EN
输出:
A_OUT
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYTRI_GATE8IS
PORT(
A_IN:
INSTD_LOGIC_VECTOR(7DOWNTO0);
EN:
INSTD_LOGIC;
A_OUT:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDTRI_GATE8;
ARCHITECTURERTLOFTRI_GATE8IS
BEGIN
PROCESS(EN,A_IN)
BEGIN
IFEN='0'THEN
A_OUT<="ZZZZZZZZ";
ELSE
A_OUT<=A_IN;
ENDIF;
ENDPROCESS;
ENDRTL;
(8)双向总线缓冲器
双向端口:
AB(inout)
使能端EN,
方向控制端DR
真值表:
EN
DR
功能
1
0
A<=B
1
1
B<=A
0
X
高阻
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYBITRIBUSIS
PORT(
DR,EN:
INSTD_LOGIC;
A,B:
INOUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDBITRIBUS;
ARCHITECTURERTLOFBITRIBUSIS
BEGIN
PROCESS(EN,DR,A,B)
BEGIN
IF(EN='0')THENA<="ZZZZZZZZ";
ELSEIF(DR='0')THENA<=B;
ELSEA<="ZZZZZZZZ";
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(EN,DR,A,B)
BEGIN
IF(EN='0')THENB<="ZZZZZZZZ";
ELSEIF(DR='1')THENB<=A;
ELSEB<="ZZZZZZZZ";
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
原理图:
(9)三人表决器
真值表:
输入
输出
A
B
C
Q
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
原理图:
(10)火灾报警系统,烟感、温感、紫外光感,两种以上探测器发出信号,系统产生报警(与(9)类似)
2.时序逻辑电路:
(1)D触发器
真值表:
数据输入D
时钟输入CLK
数据输出Q
×
0
不变
×
1
不变
0
↑
0
1
↑
1
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDFFIS
PORT(
CLK,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
);
ENDDFF;
ARCHITECTURERTLOFDFFIS
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
Q<=D;
ENDIF;
ENDPROCESS;
ENDRTL;
(2)非同步复位的D锁存器
真值表:
数据D
时钟CLK
复位CLR
输出Q
×
×
0
0
×
0/1
1
不变
0
↑
1
0
1
↑
1
0
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDFFIS
PORT(
CLK,CLR,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
);
ENDDFF;
ARCHITECTURERTLOFDFFIS
BEGIN
PROCESS(CLK,CLR)
BEGIN
IFCLR='0'THEN
Q<='0';
ELSE
IFCLK'EVENTANDCLK='1'THEN
Q<=D;
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
(3)同步复位的D锁存器
真值表:
数据D
时钟CLK
复位CLR
输出Q
×
↑
0
0
×
0/1
1
不变
0
↑
1
0
1
↑
1
0
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDFFIS
PORT(
CLK,CLR,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
);
ENDDFF;
ARCHITECTURERTLOFDFFIS
BEGIN
PROCESS(CLK,CLR)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFCLR='0'THEN
Q<='0';
ELSE
Q<=D;
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
(4)异步复位/同步置位的D触发器
真值表:
输入
输出
数据D
时钟CLK
置位PSET
复位CLR
Q
×
×
×
0
0
×
↑
0
1
1
×
0/1
1
1
不变
0
↑
1
1
0
1
↑
1
1
1
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDFF_CLRIS
PORT(
CLK,CLR,PSET,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC);
ENDDFF_CLR;
ARCHITECTURERTLOFDFF_CLRIS
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF(CLR='0')THENQ<='0';
ELSIF(CLK'EVENTANDCLK='1')THEN
IF(PSET='0')THENQ<='1';
ELSEQ<=D;
ENDIF;
ENDIF;
ENDPROCESS;
ENDRTL;
(5)JK触发器
真值表:
数据输入D
J
K
时钟输入CLK
数据输出Q
0
0
0
↑
0
1
0
0
↑
1
0/1
0
1
↑
0
0/1
1
0
↑
1
0
1
1
↑
1
1
1
1
↑
0
程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDFFIS
PORT(
CLK,J,K,D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
);
ENDDFF;
ARCHITECTURERTLOFDFFIS
BEGIN
PROCESS(CLK,J,K)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFJ='0'ANDK='0'
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