verilog文档.docx
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verilog文档.docx
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verilog文档
verilog文档.txt如果青春的时光在闲散中度过,那么回忆岁月将是一场凄凉的悲剧。
杂草多的地方庄稼少,空话多的地方智慧少。
即使路上没有花朵,我仍可以欣赏荒芜。
//-----------------------------------------------------------------------------------
//逻辑运算1
//filename:
gate4.v
//-----------------------------------------------------------------------------------
modulegate4(IN0,IN1,OUT0,OUT1,OUT2,OUT3);
inputIN0,IN1;
outputOUT0,OUT1,OUT2,OUT3;
assignOUT0=IN0&IN1;//信号赋值语句(assign)
assignOUT1=IN0|IN1;//逻辑运算符(&,|,~,^,)
assignOUT2=~IN0;//阻赛赋值(=)
assignOUT3=IN0^IN1;//两目运算符
endmodule
//-----------------------------------------------------------------------------------
//三态门2(双向端口三态总线电路的设计)
//filename:
tri_2.v
//-----------------------------------------------------------------------------------
moduletri_2(outp,ina,en);
inputina,en;
outputoutp;
assignoutp=en?
in:
b'z;//三目运算符相当于如果(en==1)为真则outp=in,
//否则outp=z
endmodule
//-----------------------------------------------------------------------------------
//比较器3
//filename:
compare.v
//-----------------------------------------------------------------------------------
modulecompare(a,b,c);
inputa,b;
outputc;
assignc=(a==b)?
a:
b;//相当于如果(a==b)条件为真,c=a,否则c=b。
endmodule
//-----------------------------------------------------------------------------------
//全加器的设计4
//filename:
adder8.v
//-----------------------------------------------------------------------------------
moduleadder8(cout,sum,ain,bin,cin);
input[7:
0]ain,bin;
inputcin;
outputcout;
output[7:
0]sum;
assign{cout,sum}=ain+bin+cin;//信号合并{,}
endmodule
//-----------------------------------------------------------------------------------
//多路选择器5
//filename:
mux41.v
//Codestyle:
usedcasestatement
//-----------------------------------------------------------------------------------
modulemux41(IN0,IN1,IN2,IN3,SEL,OUT);
input[7:
0]IN0,IN1,IN2,IN3;
input[1:
0]SEL;
output[7:
0]OUT;
wire[7:
0]IN0,IN1,IN2,IN3;//wire型
wire[1:
0]SEL;
reg[7:
0]OUT;//reg型
always@(SELorIN0orIN1orIN2orIN3)
begin//块语句(beginend)
case(SEL)//条件分支语句(caseendcase)
0:
OUT=IN0;
1:
OUT=IN1;
2:
OUT=IN2;
3:
OUT=IN3;//阻赛赋值(=)
default:
OUT<={8{1'b0}};//非阻塞型赋值(<=)
endcase
end
endmodule
//-----------------------------------------------------------------------------------
//二进制转换成BCD码6
//filename:
bin2bcd.v
//-----------------------------------------------------------------------------------
modulebin2bcd(data_in,data_out);
input[3:
0]data_in;
output[7:
0]data_out;
reg[7:
0]data_out;
always@(data_in)
begin
case(data_in[3:
1])
3'b000:
data_out[7:
1]=7'b0000000;
3'b001:
data_out[7:
1]=7'b0000001;
3'b010:
data_out[7:
1]=7'b0000010;
3'b011:
data_out[7:
1]=7'b0000011;
3'b100:
data_out[7:
1]=7'b0000100;
3'b101:
data_out[7:
1]=7'b0001000;
3'b110:
data_out[7:
1]=7'b0001001;
3'b111:
data_out[7:
1]=7'b0001010;
default:
data_out[7:
1]={7{1'b0}};//信号合并符{{}}
endcase
data_out[0]=data_in[0];
end
endmodule
//-----------------------------------------------------------------------------------
//二进制转换成格雷码7
//filename:
bin2gray.v
//-----------------------------------------------------------------------------------
modulebin2gray(DATA_IN,DATA_OUT);
input[3:
0]DATA_IN;
output[3:
0]DATA_OUT;
assignDATA_OUT[0]=DATA_IN[0]^DATA_IN[1];
assignDATA_OUT[1]=DATA_IN[1]^DATA_IN[2];
assignDATA_OUT[2]=DATA_IN[2]^DATA_IN[3];
assignDATA_OUT[3]=DATA_IN[3];
endmodule
//-----------------------------------------------------------------------------------
//二进制转换成7段码8
//filename:
bin27seg.v
//segmentencoding
//a
//+---+
//f||b
//+---+<-g
//e||c
//+---+
//d
//Outputs(data_out)active:
low
//-----------------------------------------------------------------------------------
modulebin27seg(data_in,data_out);
input[3:
0]data_in;
output[6:
0]data_out;
reg[6:
0]data_out;
always@(data_in)
begin
case(data_in)
4'b0000:
data_out=7'b1000000;//0
4'b0001:
data_out=7'b1111001;//1
4'b0010:
data_out=7'b0100100;//2
4'b0011:
data_out=7'b0110000;//3
4'b0100:
data_out=7'b0011001;//4
4'b0101:
data_out=7'b0010010;//5
4'b0110:
data_out=7'b0000011;//6
4'b0111:
data_out=7'b1111000;//7
4'b1000:
data_out=7'b0000000;//8
4'b1001:
data_out=7'b0011000;//9
4'b1010:
data_out=7'b0001000;//A
4'b1011:
data_out=7'b0000011;//b
4'b1100:
data_out=7'b0100111;//c
4'b1101:
data_out=7'b0100001;//d
4'b1110:
data_out=7'b0000110;//E
4'b1111:
data_out=7'b0001110;//F
default:
data_out=7'b1111111;
endcase
end
endmodule
//-----------------------------------------------------------------------------------
//奇偶校验电路9
//filename:
parity.v
//-----------------------------------------------------------------------------------
moduleparity(EVEN_BIT,ODD_BIT,INDATA);
input[7:
0]INDATA;
outputEVEN_BIT,ODD_BIT;
assignODD_BIT=^INDATA;//一元约简运算符相当于ODD_BIT=(INDATA[0]^INDATA[1])^
assignEVEN_BIT=~ODD_BIT;//(INDATA[2])^...
endmodule
//-----------------------------------------------------------------------------------
//8D触发器10
//filename:
ff8d.v
//-----------------------------------------------------------------------------------
moduleff8d(CLR,SET,CE,LOAD,DATA_IN,DATA_OUT,CLK);
inputCLR,SET,CE,LOAD,CLK;
input[7:
0]DATA_IN;
output[7:
0]DATA_OUT;
reg[7:
0]DATA_OUT_TEMP;
always@(posedgeCLK)
begin
if(CE==1'b1)
if(CLR==1'b1)
DATA_OUT_TEMP={8{1'b0}};
elseif(SET==1'b1)
DATA_OUT_TEMP={8{1'b1}};
elseif(LOAD==1'b1)
DATA_OUT_TEMP=DATA_IN;
end
assignDATA_OUT=DATA_OUT_TEMP;
endmodule
//-----------------------------------------------------------------------------------
//10进制计数器的设计(异步清零)11
//filename:
CNT10.v
//-----------------------------------------------------------------------------------
moduleCNT10(CLK,ENABLE,RESET,FULL,Q);
inputCLK,ENABLE,RESET;
outputFULL;
output[3:
0]Q;
REG[3:
0]QINT;
always@(posedgeRESETORposedgeCLK)
begin
if(RESET)
QINT=4'B0000;
elseif(ENABLE)
begin
if(QINT==9)
QINT=4'B0000;
else
QINT=QINT+4'B1;
end
end
assignQ=QINT;
assignFULL=(QINT==9)?
1'B1:
1'B0;
endmodule
//-----------------------------------------------------------------------------------
//模可控计数器的设计(同步加载异步清零A,异步加载异步清零B)12
//filename:
FDIV_A.vFDIV_B.V
//-----------------------------------------------------------------------------------
moduleFDIV_A(CLK,PM,DIN,DOUT,RST);
inputCLK,RESET;
input[3:
0]DIN;
outputPM;
output[3:
0]DOUT;
REG[3:
0]FULL;
REG[3:
0]QINT;
(*synthesis,keep*)WIRELD;//设定LD为仿真可测试属性
always@(posedgeCLKORnegedgeRST)
begin
if(!
RST)
begin
QINT<=0;
FULL<=0;
end
elseif(LD)
begin
QINT<=DIN;
FULL<=1;
end
else
begin
QINT=QINT+1;
FULL<=0;
end
end
assignQOUT=QINT;
assignPM=FULL;
assignLD=(QINT==4'B1111)?
1'B1:
1'B0;
endmodule
//----------------------------------------------------------------------
moduleFDIV_B(CLK,PM,DIN,DOUT,RST);
inputCLK,RESET;
input[3:
0]DIN;
outputPM;
output[3:
0]DOUT;
REG[3:
0]FULL;
REG[3:
0]QINT;
(*synthesis,keep*)WIRELD;//设定LD为仿真可测试属性
always@(posedgeCLKornegedgeRSTorposedgeLD)
begin
if(!
RST)
begin
QINT<=0;
FULL<=0;
end
else
if(LD)
begin
QINT<=DIN;
FULL<=1;
end
else
begin
QINT=QINT+1;
FULL<=0;
end
end
assignQOUT=QINT;
assignPM=FULL;
assignLD=(QINT==4'B0000)?
1'B1:
1'B0;//WHY?
endmodule
//-----------------------------------------------------------------------------------
//二分频器13
//filename:
FDIV_2.v
//
//-----------------------------------------------------------------------------------
moduleFDIV_2(CLKIN,CLKOUT);
inputCLKIN;
outputCLKOUT;
REGCLKOUT;
always@(posedgeCLK)
begin
CLKOUT=~CLKIN;
end
endmodule
//-----------------------------------------------------------------------------------
//移位寄存器的设计14
//DESCRIPTION:
Shiftregister
//filename:
shft_reg.v
//Width:
4
//Shiftdirection:
right/left(rightactivehigh)
//-----------------------------------------------------------------------------------
moduleshft_reg(CLR,SET,DIR,CE,LOAD,DATA,SI,data_out,CLK);
inputCLR,SET,CE,LOAD,DIR,SI,CLK;
input[3:
0]DATA;
output[3:
0]data_out;
reg[3:
0]TEMP;
always@(posedgeCLK)
begin
if(CE==1'b1)
if(CLR==1'b1)
TEMP={4{1'b0}};
elseif(SET==1'b1)
TEMP={4{1'b1}};
elseif(LOAD==1'b1)
TEMP=DATA;
elseif(DIR==1'b1)
TEMP={SI,TEMP[3:
1]};
else
TEMP={TEMP[2:
0],SI};
end
assigndata_out=TEMP;
endmodule
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
//自上而下的层次化设计15
//VerilogHDL:
CreatingaHierarchicalDesign
//filename:
top_ver.v
//bottom1.v
//bottom2.v
//ThisexampledescribeshowtocreateahierarchicaldesignusingVerilogHDL.
//Thefiletop_ver.visthetoplevel,
//whichcallsthetwolowerlevelfilesbottom1.vandbottom2.v.
//---------------------------------------------------------------------------
moduletop_ver(q,p,r,out);
inputq,p,r;
outputout;
regout,intsig;
bottom1u1(.a(q),
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