河工大 eda实验考试题目及答案.docx
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河工大 eda实验考试题目及答案.docx
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河工大eda实验考试题目及答案
1,设计一个带计数使能、同步复位、带进位输出的增1六位二进制计数器,计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk,clk1,en,clr:
instd_logic;
ledout:
outstd_logic_vector(6downto0);
scanout:
outstd_logic_vector(1downto0);
co:
outstd_logic);
endcounter;
architectureaofcounteris
signalcnt:
std_logic_vector(7downto0);
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic:
='0';
signalhex:
std_logic_vector(3downto0);
begin
process(clk)
begin
if(clk'eventandclk='1')then
ifen='1'then
ifclr='1'then
cnt<=(others=>'0');
else
ifcnt="00111111"then
cnt<="00000000";
co<='1';
else
cnt<=cnt+'1';
co<='0';
endif;
endif;
endif;
endif;
endprocess;
process(clk1)
begin
ifclk1'eventandclk1='1'then
scan<=notscan;
endif;
endprocess;
ledout<=notled;
scanout<="10"whenscan='0'else"01";
hex<=cnt(7downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"0001000"when"1010",
"0000011"when"1011",
"1000110"when"1100",
"0100001"when"1101",
"0000110"when"1110",
"0001110"when"1111",
"1000000"whenothers;
enda;
2、设计一个带计数使能、异步复位、带进位输出的增1二十进制计数器,计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydais
Port(clk:
inSTD_LOGIC;
clk1:
inSTD_LOGIC;
clr:
inSTD_LOGIC;
en:
inSTD_LOGIC;
co:
outSTD_LOGIC;
ledout:
outSTD_LOGIC_VECTOR(6downto0);
sel:
outSTD_LOGIC_VECTOR(1downto0));
endda;
architectureehavioralofdais
signalcnt:
std_logic_vector(7downto0):
="00000000";
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic:
='0';
signalhex:
std_logic_vector(3downto0);
begin
process(clk,clr)
begin
ifclr='1'then
cnt<=(others=>'0');
elsifclk'eventandclk='1'then
ifen='1'then
ifcnt="00001001"then
cnt<="00010000";
co<='0';
elsifcnt="00011001"then
cnt<="00000000";
co<='1';
else
cnt<=cnt+'1';
co<='0';
endif;
endif;
endif;
endprocess;
process(clk1)
begin
ifclk1'eventandclk1='1'then
scan<=notscan;
endif;
endprocess;
hex<=cnt(7downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"1000000"when"0000",
"1111111"whenothers;
ledout<=notled;
sel<="10"whenscan='0'else"01";
endehavioral;
3、设计一个带计数使能、同步复位、同步装载的可逆七位二进制计数器,计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk,clks,clr,en,stld,dir:
instd_logic;
din:
instd_logic_vector(6downto0);
ledout:
outstd_logic_vector(6downto0);
scanout:
outstd_logic_wector(1downto0);
endcounter;
architectureaofcounteris
signalcnt:
std_logic_vector(6downto0);
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic;
signalhex:
std_logic_vector(3downto0);
begin
process(clk,clr)
begin
ifclk'eventandclk='1'then
ifclr='1'then
cnt<=(others=>'0');
else
ifstld='0'then
cnt<=din;
elsifen='1'then
ifdir='1'then
ifcnt=”01111111”then
cnt<=“00000000”;
co<=’1’;
else
cnt<=cnt+1;
endif;
else
ifcnt=”00000000”then
cnt<=“01111111”;
co<=’1’;
else
cnt<=cnt-1;
endif;
endif;
endif;
endif;
Endif;
endprocess;
process(clks)
begin
ifclks'eventandclks='1'then
scan<=notscan;
endif;
endprocess;
ledout<=notled;
scanout<="10"whenscan='0'else"01";
hex<='0'&cnt(6downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"0001000"when"1010",
"0000011"when"1011",
"1000110"when"1100",
"0100001"when"1101",
"0000110"when"1110",
"0001110"when"1111",
"1000000"whenothers;
Enda;
4、设计一个带计数使能、异步复位、异步装载、可逆计数的通用计数器。
计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
generic(count_value:
integer:
=9);
port(clk,clr,en,load,dir:
instd_logic;
data_in:
inintegerrange0tocount_value;
count:
outintegerrange0tocount_value;
ledout:
outstd_logic_vector(6downto0));
endcounter;
architectureaofcounteris
signalcnt:
integerrange0tocount_value;
signalled:
std_logic_vector(6downto0);
begin
process(load,clk)
begin
ifclr='1'then
cnt<=0;
else
ifload='1'thencnt<=data_in;
elsif(clk'eventandclk='1')then
ifen='1'then
ifdir='1'then
ifcnt=count_valuethen
cnt<=0;
else
cnt<=cnt+1;
endif;
else
ifcnt=0then
cnt<=count_value;
else
cnt<=cnt-1;
endif;
endif;
endif;
endif;
endif;
endprocess;
count<=cnt;
ledout<=notled;
withcntselect
led<="1111001"when1,
"0100100"when2,
"0110000"when3,
"0011001"when4,
"0010010"when5,
"0000010"when6,
"1111000"when7,
"0000000"when8,
"0010000"when9,
"1000000"when0,
"1111111"whenothers;
Enda;
5、设计一个具有16分频、8分频、4分频和2分频功能的分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityclkdivis
port(clk:
instd_logic;
clk_div2:
outstd_logic;
clk_div4:
outstd_logic;
clk_div8:
outstd_logic;
clk_div16:
outstd_logic);
endclkdiv;
architecturertlofclkdivis
signalcount:
std_logic_vector(3downto0);
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(count="1111")then
count<=(others=>'0');
else
count<=count+1;
endif;
endif;
endprocess;
clk_div2<=count(0);
clk_div4<=count
(1);
clk_div8<=count
(2);
clk_div16<=count(3);
endrtl;
6、设计一个正负脉宽相等的通用分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounterIS
GENERIC(count_value:
INTEGER:
=15);
PORT(clk,clr,en:
INSTD_LOGIC;
count:
OUTSTD_LOGIC);
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALcnt:
INTEGERRANGE0TOcount_value;
SIGNALco:
STD_LOGIC;
SIGNALcount1:
STD_LOGIC;
BEGIN
PROCESS(clk,clr)
BEGIN
IFclr='1'THEN
cnt<=0;
ELSIF(clk'EVENTANDclk='1')THEN
IFen='1'THEN
IFcnt=count_valueTHEN
cnt<=0;
co<='1';
ELSE
cnt<=cnt+1;
co<='0';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(co)
BEGIN
IF(co'EVENTANDco='1')THEN
count1<=NOTcount1;
ENDIF;
count<=count1;
ENDPROCESS;
ENDa;
7、设计一个正负脉宽可控的16分频的分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfen_pinis
port(clk:
instd_logic;
din:
instd_logic_vector(1downto0);
count:
outstd_logic);
endfen_pin;
architecturebehaveoffen_pinis
signalco:
std_logic;
begin
count<=co;
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'eventandclk='1')then
if(cnt="1111")then
cnt:
="0000";
co<=notco;
elsif(cnt=din)then
co<=notco;
cnt:
=cnt+'1';
elsecnt:
=cnt+'1';
endif;
endif;
endprocess;
endbehave;
8、根据需要设计一个分频器:
可以控制实现四种分频形式:
第一种:
8分频、第二种:
10分频、第三种:
15分频、第四种:
16分频,其中8分频和16分频为正负脉宽相等的分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(clk:
instd_logic;
en:
instd_logic_vector(1downto0);
cout:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endfenpin;
architecturedgnfenpinoffenpinis
signalled:
std_logic_vector(6downto0);
signalhex:
std_logic_vector(3downto0);
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'eventANDclk='1')then
if(en="00")then
if(cnt>="1000")then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
cout<=cnt
(2);
elsif(en="01")then
if(cnt>="1010")then
cnt:
="0000";
cout<='1';
else
cnt:
=cnt+'1';
cout<='0';
endif;
elsif(en="10")then
if(cnt>="1110")then
cnt:
="0000";cout<='1';
else
cnt:
=cnt+'1';cout<='0';
endif;
else
if(cnt>="1111")then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
cout<=cnt(3);
endif;
endif;
endprocess;
ledout<=notled;
withenselect
led<="0000000"when"00",
"0001000"when"01",
"0001110"when"10",
"1000000"when"11",
"1111111"whenothers;
enddgnfenpin;
9、设计一个M序列发生器,M序列为“11100111”
LIBRARYIEEE;
USEIEEE.STD_logic_1164.all;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSEQIS
PORT(CLK:
INSTD_logic;
FOUT:
OUTSTD_logic);
ENDSEQ;
ARCHITECTUREBEHAVEOFSEQIS
SIGNALCNT:
STD_logic_VECTOR(2DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFCNT="111"THEN
CNT<="000";
ELSE
CNT<=CNT+'1';
ENDIF;
ENDIF;
ENDPROCESS;
WITHCNTSELECT
FOUT<='1'WHEN"000",
'1'WHEN"001",
'1'WHEN"010",
'0'WHEN"011",
'0'WHEN"100",
'1'WHEN"101",
'1'WHEN"110",
'1'when"111",
'0'WHENOTHERS;
endBEHAVE;
10、设计一个彩灯控制器,彩灯共有21个,每次顺序点亮相邻的3个彩灯,如此循环执行,循环的方向可以控制
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycaidengis
port(clk,reset:
instd_logic;
l_r:
instd_logic;----控制循环方向;
output:
outstd_logic_vector(15downto0));---输出
endentity;
architectureartofcaidengis
signalq:
std_logic_vector(15downto0);
begin
process(clk,reset,l_r,q)
begin
ifreset='1'then
q<="0000000000000000";
elsifclk'eventandclk='1'then
ifl_r='1'then----表示向右循环;
ifq="0000000000000000"then
q<="1110000000000000";
elseq<=q(0)&q(15downto1);
endif;
else----向左循环;
ifq="0000000000000000"then
q<="0000000000000111";
elseq<=q(14downto0)&q(15);
endif;
endif;
endif;
output<=q;
endprocess;
endart;
11、设计一个具有左移、右移控制,同步并行装载和串行装载的8位串行移位寄存器
library
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